Error

[Altera_Forum]

I vonder what is wrong in this code: 

 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.ALL; entity uppgift_vhdl_3a is port ( Sys_clk, reset_n, knapp_in_1 : in std_logic; lysdiod_ut : out std_logic_vector(2 downto 0) ); End entity uppgift_vhdl_3a; architecture rtl of uppgift_3a_debugg is ---- internal signal declaration signal signal_raknarvarde : std_logic_vector(2 downto 0); signal old_knapp_in_1 :std_logic; begin process (sys_clk) begin if (rising_edge(sys_clk)) then if reset_n = '0' then ---Reset the counter to 0 23 signal_raknarvärde <= "000"; 25 elsif knapp_in_1 = '1'; then signal_raknarvarde <= signal_raknarvarde + '1'; else signal_raknarvarde <= signal_raknarvarde; end if; end if; end process; 36 :cry:....?   Error come up..   Error (10500): VHDL syntax error at uppgift_3a.vhd(23) near text ¤  Error (10500): VHDL syntax error at uppgift_3a.vhd(23) near text "¤"; expecting "(", or "'", or "."  Error (10500): VHDL syntax error at uppgift_3a.vhd(25) near text ";"; expecting "then"  Error (10522): VHDL Syntax error at uppgift_3a.vhd(36): experienced unexpected end-of-file ; expecting "end", or "(", or an identifier, or a concurrent statement

[Altera_Forum]

Not sure about line 23, try renaming your signal name without the "ä" and use "a" instead. (note the accent marks) 

 line 25 should not have the ';' character between "if" and "then".  Fixing both of these might clear up your problems.

[Altera_Forum]

--- Quote Start ---  Not sure about line 23, try renaming your signal name without the "ä" and use "a" instead. (note the accent marks)   line 25 should not have the ';' character between "if" and "then".   Fixing both of these might clear up your problems.  --- Quote End ---       Thanks :rolleyes:. Do you know what this is ?     Error (10522): VHDL Syntax error at uppgift_3a.vhd(36): experienced unexpected end-of-file ; expecting "end", or "(", or an identifier, or a concurrent statement

[Altera_Forum]

Ahh, didn't notice what you were missing - add 

 end rtl;  at the end. You need to close out your architecture.