Hey, Im just starting to learn to use Quartus II, and I keep getting a syntax error when I try to compile this at line 3
module mux2to1_8bit(SW, LEDR);
input [17:0]SW;
wire [7:0]X, [7:0]Y, [7:0]M, [0:0]Sel; <--- The error leads here
output [7:0]LEDR;
assign M[0] = (~Sel & X[0]) | (Sel & Y[0]);
assign M[1] = (~Sel & X[1]) | (Sel & Y[1]);
assign M[2] = (~Sel & X[2]) | (Sel & Y[2]);
assign M[3] = (~Sel & X[3]) | (Sel & Y[3]);
assign M[4] = (~Sel & X[4]) | (Sel & Y[4]);
assign M[5] = (~Sel & X[5]) | (Sel & Y[5]);
assign M[6] = (~Sel & X[6]) | (Sel & Y[6]);
assign M[7] = (~Sel & X[7]) | (Sel & Y[7]);
assign SW[7:0] = X;
assign SW[15:8] = Y;
assign SW[17] = Sel;
assign LEDR = M;
endmodule
Error (10170): Verilog HDL syntax error at mux2to1_8bit.v(3) near text "["; expecting an identifier
Any suggestions?
thanks
