Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15540 Discussions

Expecting IDENTIFIER in Signals

Honored Contributor II

Hey all, 


I've googled this problem and it always seems to be a missing semicolon or paren somewhere, but I've looked over my code and I see nothing. I know it's going to be simple and I will feel stupid, but I am just learning VHDL and going by the book. What is wrong with my signal declaration here? 


library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -- Processor -- Mainly based off of Ch 4 in the CArch book entity jaggy is port (CLK, pwr, instrin: in std_logic); end jaggy; architecture struct of jaggy is -- Signals to interconnect components signal( d1, d2, d3, d4, d5, t1 : std_logic; a1 : std_logic_vector(7 downto 0); i1 : std_logic_vector(31 downto 0) ); begin -- Entities will be instantiated here -- Program Counter pc: entity work.prog_count port map(addrin => i1, addrout => a1); -- Instruction Memory im: entity work.instr_mem port map(PC => a1, instr => i1); -- Register File reg: entity work.reg_file port map(instrin => i1, dataout1 => d1, dataout2 => d2, memout => d3, datain1 => d4, datain2 => d5); -- ALU alu: entity work.arith_log_unit port map(datain1 => d1, datain2 => d2, dataout => d4); -- Data Memory dm: entity work.data_mem port map(addrin => d4, datain => d3, dataout => d5); -- Control Unit cu: entity work.contr_unit port map(t1); end struct;  


** Error: D:/jaggy.vhd(14): near "(": (vcom-1576) expecting IDENTIFIER.
0 Kudos
1 Reply
Honored Contributor II



The error is because of the signal declaration. 

Provide individual signal declaration like, 

signal d1, d2, d3, d4, d5, t1 : std_logic; signal a1 : std_logic_vector(7 downto 0); signal i1 : std_logic_vector(31 downto 0);  


Best Regards 

Vikas Jathar  

Intel Customer Support – Engineering 

(Under Contract to Intel)