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Altera_Forum
Honored Contributor I
998 Views

MAX10 ADC user defined output simulation in Cadence NCSIM

I'm trying to simulate user-defined ADC output using Cadence NCsim. 

Now, I used defparam to parameterized enable_usr_sim, reference_voltage_sim and simfilename_ch0-16. 

The ADC model works well when fixed data(enable_usr_sim = 0) output is used. 

When I used user defined output (enable_usr_sim = 1), 

output data is only '0'. 

 

I'm suspecting that the feature might not be applicable to other simulator than modelsim. 

Is user defined ADC output feature can be simulate other than modelsim? 

 

Thanks in advance for answering!
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3 Replies
Altera_Forum
Honored Contributor I
42 Views

Did you create the separate text file needed to create user defined output for the simulation? If so, can you post it?

Altera_Forum
Honored Contributor I
42 Views

 

--- Quote Start ---  

Did you create the separate text file needed to create user defined output for the simulation? If so, can you post it? 

--- Quote End ---  

 

 

I basically try the setting in the manual. 

I used 2.5 as reference voltage. 

 

1 0.2 2 0.5 3 0.8 4 1.1 5 1.4 

 

By the way, 

I used dual ADC IP core. 

 

Thank you for the reply!
Altera_Forum
Honored Contributor I
42 Views

 

--- Quote Start ---  

I basically try the setting in the manual. 

I used 2.5 as reference voltage. 

 

1 0.2 2 0.5 3 0.8 4 1.1 5 1.4 

 

By the way, 

I used dual ADC IP core. 

 

Thank you for the reply! 

--- Quote End ---  

 

 

 

I already figure out the problem. 

I remove the defparam for reference_voltage_sim. 

Yet, I'm still puzzled does it mean 65536 = 2.5V?
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