Good Day,I've had a DK-SOC-10AS066S-A dev kit with a 10AS066N3F40E2SG device in it for quite a few months. I'm just now starting to use it on a POC project (at Intel). I'm also doing a Xilinx Zedboard (Zynq7000) implementation of the same design. The details of the project don't matter right now. It turns out that I'm very at home in the Xilinx tools (both ISE and Vivado), but am more of a noob with the Altera toolchain. I'm starting with the easiest FPGA project I can reasonably exercise the user I/O with (e.g. LEDs, buttons, etc.). For example, consider the following module decl: module AriaTest1( input clk, input rst, output led ); Now, I want to attach the system clock to the clk input, reset to rst, and one of the leds to the led output. Pretty straightforward. With Xilinx, I know that I need to make tweaks to individual config files (different syntax per tool, but same principle). In the docs, I have been provided a reference for which pins map to each I/O device along with a default config file for my board, the syntax of the config file, and examples showing how to use said syntax. I'm having a bit of a problem figuring out how to do the same with Quartus, and am sure I'm just being ignorant. I've looked through various docs, but as of yet, haven't found what I need. I've also looked through examples in the downloadable content Altera provides for the dev kit, and am drawing a blank. The best I can figure is that the settings are stored in the qsf file. However, at the moment, my qsf file only has some general config setup; no I/O related. When I puruse the tools in Quartus, it almost seems like I should be using the PIN planner, but haven't yet learned how to use it. Are my findings correct? Is it just a matter of me reading the user guide info on the pin planner...or is their another or easier way...like there is with Xilinx tools. Specifically: - Is there a qsf file (assuming that's the right file for these settings) with all of the Aria 10 dev kit I/O clearly identified, so I can use it as a template for future projects? If so, where might I find this? - Is there another tool besides the pin planner that I should be using for such simple I/O config? - Related question: When I setup my project, I of course have to config the device itself. I've done that with the Device dlg box. It has two tabs, one for Device, and one for Board. I was expecting to find my board on the board list, but for the most part, all I have are Cyclone V boards. I know with Xilinx I had to install board files for the Zedboard. Is there something analogous for this Arria10 dev kit? Again, I looked through the downloadable content, and didn't find anything other than the 3 part downloadable that allows you to add the Arria10 devices. Are their board specific files that I need to install to find my board on that tab, or should I just be sticking to configuring by the device tab? Any help would be appreciated. I'm sure once I dive in, I'll get just as comfortable with Quartus as I am with the Xilinx tools...but for now, I'm scratching my head a bit. It seems a bit harder than I would expect it to be. Thanks, Dave
Hi,--- Quote Start --- - Is there a qsf file (assuming that's the right file for these settings) with all of the Aria 10 dev kit I/O clearly identified, so I can use it as a template for future projects? If so, where might I find this? --- Quote End --- In package which comes with the Dev kit there should be reference design called "Golden Top Design". There you can find all pin assigments. --- Quote Start --- - Is there another tool besides the pin planner that I should be using for such simple I/O config? --- Quote End --- The easiest way to make pin location and standart assigments is to use pin planner. After running Analysis and Synthesis in Pin planner you should see Node names from your top design file. Enter location assigments in "Location" column and standart assigments in "I/O standart" column. Also you can import them from another project (Assigments-> Import Assigments) or create your own .tcl script with pin assigments ect.
Thanks for the pointer and advice. At least I won't be searching for another tool besides the pin planner.So, I'm still a bit confused, as I don't see all the LEDs on the board in this qsf file. According to the docs, this board has 4 user controlled LEDs for the FPGA, and 4 for the HPS. That said, I'd expect to find a total of 8 pin assignments. I don't. I only find USER_LED_HPS2 and USER_LED_HPS3. I have a feeling that the FPGA LEDs (and other IO) are labeled as FPGAIOxx_x in the pin assignments, but have no idea how to map these to specific I/O components. I also don't know where the other 2 HPS LED pin assignments are. Of course, I have similar issues with the switches and push buttons. Am I missing something? As before, I've searched through the docs, but as of yet, have seen nothing that helps. Thanks, Dave
OK....I was about to open the golden top design before sending my last update. I should have. The golden_top module does provide the mapping between the FPGA I/O components and their names. For example, FPGAIO_P = USER_LED_FPGA. So, that at least answers part of my remaining confusion. I'm still not clear on why there are only two HPS_LED pin assignments, when the board has for HPS LEDs. I guess I'll continue to explore the golden design while waiting for somebody to possible clarify.DAve
Hey Dave,The Altera tools and Xilinx tools can both be scripted pretty easily with Tcl. Have you used Vivado's unmanaged constraints files? I've just started tinkering with the Xilinx tools ... https://github.com/d-hawkins/hdl https://github.com/d-hawkins/hdl/tree/master/boards/xilinx/digilent_arty/constraints https://github.com/d-hawkins/hdl/tree/master/boards/xilinx/digilent_arty/blinky/scripts I've posted numerous Quartus examples to this group .. https://www.alteraforum.com/forum/showthread.php?t=45927 https://www.alteraforum.com/forum/showthread.php?t=43992 Download them, follow the readme.txt instructions, and then look at the synth.tcl script that in turn runs constraints files. You'll get the hang of it quick enough. Cheers, Dave