External Memory Interfaces clock Critical Warning

[Altera_Forum]

Hi,ALL 

I'm trying to TimeQuest my design,but I have Critical Warings like this:   "Critical Warning: Clocks driving the CK pins, write clocks pins and write data pins must use the same clock tree type, either all global clocks or all regional/dual-regional clocks Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions"   So my question is: Why the colcks must use the same colck tree type,and which type is better?

[Altera_Forum]

Globals fan out to the entire chip, but there are fewer of them and they have a longer delay(which is seldom a big deal, as skew is the main concern for globals). There are more regionals but they don't span the whole device(there are dual-regionals which do expand.) My guess is either one would work for your case. Also, I'm guessing there are transfers between the two domains. If they're on the same type of network, then the edges nicely line up, but on different networks you get large skew, and whatever interface you're doing does not want that.

[Altera_Forum]

Thank you, Rysc 

From the Critical Warning,I guess the TimeQuest can't analysis the designs between two clock tree types.Because my design is bad,but the TimeQuest report is good.I guess that the TimeQuest doesn't report the fact.

[Altera_Forum]

TimeQuest can properly analyze transfers between different clock tree types, and I see it done all the time. I think this is a message from the IP you're using(a memory controller?). The ports it's talking about are all outputs, so I believe it's saying it can meet your requirements if all the outputs are on the same clock tree type(i.e. they will all have about the same delay). They may not be doing true static timing analysis between these I/O, and just saying that as long as it's layed out correctly, we know it works.

[Altera_Forum]

I may understand the meaning of the Waring and Report. 

Thank you !