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Hi,
Have spent a lot of time trying to get used to flow of new (to me) quartus/modelsim. (ver 11) About there now,,,:confused: attempting to simulate the FFT IP, using the test bench that is so kindly generated, but get the following error # Fatal error in Process memory at C:/altera/11.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39614# which looks a bit out of my control..... Anyone had this or similar? Can anyone give me a nudge in the right direction? Regards Pete BLink Copied
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If I understand right, the error is in
while not endfile(m_mem_data_file) loop
Which refers to reading in a memory initialization file, which has apparently problems.
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FvM --
yes,thanks for that. By changing build order, did get that line indicated, so I guess I will need to hard code my data into the test bench? thanks again thepancake -- thanks,have done that,,,- Mark as New
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Hi all,
so I manually moved the initialisation (real and imaginary data) text files to the simulation folder and it works! I had assumed that this all done by 'native link magic' , and perhaps one day it will I do intend to detail this so it can be shared, but I must push on with 'real' work now. anyone looking at this thread in a few weeks from now, wanting conclusion, please do post a 'nag' in this thread to remind me as I will forget!!!- Mark as New
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you can add those text files to the NativeLink window where you add the test bench file and Quartus will copy them over to the simulation directory when you run Tools > Run EDA Sim > EDA RTL Sim
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thanks, yes I see
If only the documentation (quick start guide) didn't clearly state ' no nativelink settings ' still, and this is for all the folks still mourning the loss of old built in simulator, -- modelsim is definately worth the learning curve
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