FIFO synthesized away but simulates fine

[Altera_Forum]

I'm having a problem where I have instantiated a FIFO in my design. When I compile the design it tells me the RAM module inside the FIFO has been synthesized away but when I take the exact same design into ModelSim, it simulates exactly how I would expect. 

 Is there some way to tell the compilation tool that the FIFO's outputs really are driving something and not to synthesize it away? Or is it possibly another problem I cannot figure out?  Thanks in advance.

[Altera_Forum]

--- Quote Start ---  Or is it possibly another problem I cannot figure out?   --- Quote End ---    Its another problem you have not yet figured out.  Get Quartus to generate a .vo or .vho output file for the synthesized design, and then simulate that in Modelsim.  If you have a decent testbench, you should be able to determine the difference between your original HDL file, and the synthesized logic.  Alternatively, (or in addition) use SignalTap within the hardware to check that each interface is working correctly.  Cheers, Dave

[Altera_Forum]

I can definately tell it has synthesized away most of my design, I just don't know why. What is the likely reason it would do this and why does simulation work?

[Altera_Forum]

Synthesis removes all design parts that are useless in hardware terms because they don't contribute to existing output signals. In functional simulation, you can still watch their internal states. 

 The reason, why a design entity is functionless may not be obvious at first sight. It can be e.g. an unconnected clock or reset signal, or a missing transition in a state machine. If you read the synthesis report thoroughly, you should be able to detect where the removal takes a start.

[Altera_Forum]

Oh duh, Thank you FvM. You worded it in a perfect way to get it through my dumb head. Because my design isn't quite complete, the things in the FIFO are not read externally from the submodule so it just synthesized the FIFO and the submodule away...