Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
934 Views

FPGA power consumption

Hey guys, I'm doing a comparison of performance of FPGAs and GPUs, right now I'm looking at the power consumption part. 

So I use the PowerMonitor.exe provided by Arria10 package, and the power doesn't seem to change much whether it's running data or not, 

it pretty much stays the same after the FPGA's configuration.  

Does this means that it needs power to sustain the configuration and whether it's being used to do computation doesn't effect it much? 

Also because the frequency is set after configuration?  

Thanks!
0 Kudos
6 Replies
Altera_Forum
Honored Contributor I
51 Views

The power consumption will definitely change during computation; however, your kernel might be too fast/short for the reading to show up, or the the provided power monitor might not actually work correctly. I have written my own power measurement functions for non-reference boards based on the manufacturers' API, and I have seen differences up to 30 Watts between idle (but configured) and computing states on the FPGA.

Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

The power consumption will definitely change during computation; however, your kernel might be too fast/short for the reading to show up, or the the provided power monitor might not actually work correctly. I have written my own power measurement functions for non-reference boards based on the manufacturers' API, and I have seen differences up to 30 Watts between idle (but configured) and computing states on the FPGA. 

--- Quote End ---  

 

Hi HRZ  

Thanks for the reply. I read your paper on Evaluating and Optimizing OpenCL Kernels for High Performance Computing with FPGAs, it has been really helpful. 

In the paper, the power measurements you gave include everything like on-board memory, so you are not subtracting the idle power from computing states power right? 

Thanks. 

 

Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

In the paper, the power measurements you gave include everything like on-board memory, so you are not subtracting the idle power from computing states power right? 

Thanks. 

--- Quote End ---  

 

 

That one is different from what I mentioned above. The Terasic DE5-Net board does not have a power sensor, so I had to resort to estimating the power consumption based on the power consumption of the FPGA extracted from Quartus and the maximum power consumption of the memory module. What Quartus gives you is an estimation of the static power usage (close to idle configured power) and dynamic power usage with assumption of 12.5% toggling rate. I used static + dynamic + memory power consumption in this case as an estimation of total power consumption of the FPGA board, for meaningful comparison with the power consumption of CPU (chip only) and GPU (full board). Excluding the idle power (static power) of the FPGA board will not give you meaningful results because in many designs, the static power is actually higher than the dynamic power. 

 

Right now I mostly rely on my Arria 10 board which includes a power sensor, and read the sensor in the same way as the sensor on the CPU or GPU boards since power measurement in this way will be much more accurate than estimating with Quartus. Some people also use an external power meter on the wall, and subtract the idle power of the system from the system power consumption during FPGA execution, to extract the total power consumption of the FPGA board, but this will never be as accurate as reading the power sensor on the FPGA board (if any).
Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

That one is different from what I mentioned above. The Terasic DE5-Net board does not have a power sensor, so I had to resort to estimating the power consumption based on the power consumption of the FPGA extracted from Quartus and the maximum power consumption of the memory module. What Quartus gives you is an estimation of the static power usage (close to idle configured power) and dynamic power usage with assumption of 12.5% toggling rate. I used static + dynamic + memory power consumption in this case as an estimation of total power consumption of the FPGA board, for meaningful comparison with the power consumption of CPU (chip only) and GPU (full board). Excluding the idle power (static power) of the FPGA board will not give you meaningful results because in many designs, the static power is actually higher than the dynamic power. 

 

Right now I mostly rely on my Arria 10 board which includes a power sensor, and read the sensor in the same way as the sensor on the CPU or GPU boards since power measurement in this way will be much more accurate than estimating with Quartus. Some people also use an external power meter on the wall, and subtract the idle power of the system from the system power consumption during FPGA execution, to extract the total power consumption of the FPGA board, but this will never be as accurate as reading the power sensor on the FPGA board (if any). 

--- Quote End ---  

 

Got you thanks!!
Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

That one is different from what I mentioned above. The Terasic DE5-Net board does not have a power sensor, so I had to resort to estimating the power consumption based on the power consumption of the FPGA extracted from Quartus and the maximum power consumption of the memory module. What Quartus gives you is an estimation of the static power usage (close to idle configured power) and dynamic power usage with assumption of 12.5% toggling rate. I used static + dynamic + memory power consumption in this case as an estimation of total power consumption of the FPGA board, for meaningful comparison with the power consumption of CPU (chip only) and GPU (full board). Excluding the idle power (static power) of the FPGA board will not give you meaningful results because in many designs, the static power is actually higher than the dynamic power. 

 

Right now I mostly rely on my Arria 10 board which includes a power sensor, and read the sensor in the same way as the sensor on the CPU or GPU boards since power measurement in this way will be much more accurate than estimating with Quartus. Some people also use an external power meter on the wall, and subtract the idle power of the system from the system power consumption during FPGA execution, to extract the total power consumption of the FPGA board, but this will never be as accurate as reading the power sensor on the FPGA board (if any). 

--- Quote End ---  

 

Would you know does the sensor on Arria10 includes the power of the memory?  

The options includes VCCRAM/ VCCMEM...etc so I assume the top one VCC includes everything? 

Not sure what does the others stand for, nothing mentioned in the manual.
Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

Would you know does the sensor on Arria10 includes the power of the memory?  

The options includes VCCRAM/ VCCMEM...etc so I assume the top one VCC includes everything? 

Not sure what does the others stand for, nothing mentioned in the manual. 

--- Quote End ---  

 

 

These options that you are talking about seem to be the supply volatge of different componenets on the board. I am not really sure what they mean in case of your board. My board has an actual power sensor that directly reports Wattage for all of the board.
Reply