Hello,
I am new to FPGA's and i am trying to learn to work with them. while i was trying to run an rtl simlation on questasim(free ver) i encountered the following in questasim:
# Reading pref.tcl
# // Questa Intel Starter FPGA Edition-64
# // Version 2023.3 win64 Jul 17 2023
# //
# // Copyright 1991-2023 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# do inv_run_msim_rtl_verilog.do
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# Error in macro ./inv_run_msim_rtl_verilog.do line 2
# Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023
# vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver
# Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver".
# No such file or directory. (errno = ENOENT)
# while executing
# "error [FixExecError $msg]"
# (procedure "vmap" line 29)
# invoked from within
# "vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver"
i can not find anything called altera_ver anywhere. i was getting a different error before which was :
C:/IntelFPGA_lite/23.1std/questa_fse/win64/vsim.exe this did not work and after running the quartus # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" tb_inv.v
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs=""+acc"" tb_inv.v
# Start time: 12:07:15 on Feb 06,2025
# ** Error (suppressible): (vsim-19) Failed to access library 'tb_inv' at "tb_inv".
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./inv_run_msim_rtl_verilog.do PAUSED at line 12
now iam stuck here for past few hours can you please help me out. i am just trying to run a simple inverter program
i have already added the quartus and questa directories to path. i tried to recompile the simulation libraries but there was another error there.
連結已複製
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