False latching error

[Altera_Forum]

Hi, 

When I synthesize my design in QUARTUS II I get the error: Error (10166): SystemVerilog RTL Coding error at hmon_eeprom.sv(59): always_comb construct does not infer purely combinational logic.  the always_comb construct in my design is simply a "case" statement on a parameter. In the case statement i set 4 output to different values in each value of the parameter, AND i have a default value at the end of the case statement. Despite the default value, i still get the error of latches found by synthesis in an always_comb construct.  Does anyone know what is the problem and how can I solve it? I'm stuck in this issue.  Thanks.

[Altera_Forum]

Looks like not all output bits (or internal signals) are set unconditionally. Show the code.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

The code needs to infer latches for bus2ip_data which isn't assigned in all case items.  

You can enforce pure combinational logic by assigning the default values unconditionally in front of the case statement.  I don't see a purpose of using casez.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

Hi 

 Assigning bus2ip_data in all cases resolved it.  Thanks again.