# ** Fatal: Unexpected signal: 11.

[RichardMoeller]

I am randomly getting the error when using Questa 21.1 

# ** Fatal: Unexpected signal: 11.

 This is occurring during automated regression tests and the same base is recompiled multiple times with no errors. 

# vsim -voptargs=""+acc"" -fsmdebug -t ps -L work -L altera_lnsim_ver -L altera_mf_ver -L 220model_ver tb_amp_cntrl_fpga_top -l log_tc.txt 
# Start time: 03:51:58 on Nov 26,2021
# ** Note: (vsim-3812) Design is being optimized...
# ** Fatal: Unexpected signal: 11.
# ../../tb/models/altera_ip/alt_remote_update_sim_model.v(1): Vopt Compiler exiting
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0.
# Error loading design
Error loading design

[RichardTanSY_Intel]

Hi @RichardMoeller 

This might be a potential bug. 

Could you share your design and provide the steps to duplicate the error? 

If your design can not be shared publicly, I will send you a separate email. 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[RichardTanSY_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.