Fibonacci Code

[Altera_Forum]

This is a Fibonacci code that i made. but it doesn't compile in Quartus II 9.0. but it compile on ModelSim.i need to run on Ciclone II. Could you help me? 

 module fib( LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8);  reg [7:0] i;  reg [7:0] prev; reg [7:0] actual; reg [7:0] sum;  output reg[7:0] LED1; output reg[7:0] LED2; output reg[7:0] LED3; output reg[7:0] LED4; output reg[7:0] LED5; output reg[7:0] LED6; output reg[7:0] LED7; output reg[7:0] LED8;  //parameter ON = 1'b1; //parameter OFF = 1'b0;  always # 5 begin  sum = actual + prev; prev = actual; actual = sum;  end  always# 6 begin    if (sum == 8'd0)  begin  assign LED1 = 1'b0;  assign LED2 = 1'b0;  assign LED3 = 1'b0;  assign LED4 = 1'b0;  assign LED5 = 1'b0;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd1)  begin  assign LED1 = 1'b1;  assign LED2 = 1'b0;  assign LED3 = 1'b0;  assign LED4 = 1'b0;  assign LED5 = 1'b0;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd2)  begin   assign LED1 = 1'b0;  assign LED2 = 1'b1;  assign LED3 = 1'b0;  assign LED4 = 1'b0;  assign LED5 = 1'b0;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd3)  begin   assign LED1 = 1'b1;  assign LED2 = 1'b1;  assign LED3 = 1'b0;  assign LED4 = 1'b0;  assign LED5 = 1'b0;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd5)  begin   assign LED1 = 1'b1;  assign LED2 = 1'b0;  assign LED3 = 1'b1;  assign LED4 = 1'b0;  assign LED5 = 1'b0;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd8)  begin   assign LED1 = 1'b0;  assign LED2 = 1'b0;  assign LED3 = 1'b0;  assign LED4 = 1'b1;  assign LED5 = 1'b0;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd13)  begin   assign LED1 = 1'b1;  assign LED2 = 1'b0;  assign LED3 = 1'b1;  assign LED4 = 1'b1;  assign LED5 = 1'b0;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd21)  begin   assign LED1 = 1'b1;  assign LED2 = 1'b0;  assign LED3 = 1'b1;  assign LED4 = 1'b0;  assign LED5 = 1'b1;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd34)begin   assign LED1 = 1'b0;  assign LED2 = 1'b0;  assign LED3 = 1'b1;  assign LED4 = 1'b0;  assign LED5 = 1'b0;  assign LED6 = 1'b1;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd55)  begin   assign LED1 = 1'b1;  assign LED2 = 1'b1;  assign LED3 = 1'b1;  assign LED4 = 1'b0;  assign LED5 = 1'b1;  assign LED6 = 1'b1;  assign LED7 = 1'b0;  assign LED8 = 1'b0;  end    else if(sum == 8'd89)begin   assign LED1 = 1'b1;  assign LED2 = 1'b0;  assign LED3 = 1'b0;  assign LED4 = 1'b1;  assign LED5 = 1'b1;  assign LED6 = 1'b0;  assign LED7 = 1'b1;  assign LED8 = 1'b0;  end    else if(sum == 8'd144)  begin   assign LED1 = 1'b0;  assign LED2 = 1'b0;  assign LED3 = 1'b0;  assign LED4 = 1'b0;  assign LED5 = 1'b1;  assign LED6 = 1'b0;  assign LED7 = 1'b0;  assign LED8 = 1'b1;  end    else if (sum == 8'd233)  begin   assign LED1 = 1'b1;  assign LED2 = 1'b0;  assign LED3 = 1'b0;  assign LED4 = 1'b1;  assign LED5 = 1'b0;  assign LED6 = 1'b1;  assign LED7 = 1'b1;  assign LED8 = 1'b1;  end  end  initial begin  $monitor("Time = %g Sum = %d", $time, sum);  prev = 8'd0; actual = 8'd1; sum = 8'd0; i = 8'd60; # 5$display("Time= %g Sum = %d", $time, 1); # i $finish; end  endmodule  thanks for all!

[Altera_Forum]

The module is completely asynchronous. You really need a clock and hopefully a reset. 

 try this: module fib( input clk, input reset_n, output LED1, output LED2, output LED3, output LED4, output LED5, output LED6, output LED7, output LED8 ); reg prev; reg actual; assign LED1 = {7'd0,actual}; assign LED2 = {7'd0,actual}; assign LED3 = {7'd0,actual}; assign LED4 = {7'd0,actual}; assign LED5 = {7'd0,actual}; assign LED6 = {7'd0,actual}; assign LED7 = {7'd0,actual}; assign LED8 = {7'd0,actual}; always @(posedge clk or negedge reset_n) begin if(!reset_n) begin prev <= 8'd0; actual <= 8'd1; end else begin prev <= actual; actual <= actual + prev; end endmodule

[Altera_Forum]

Modfied for only 8 outputs. You need to make your pin assignments in Quartus as LED[0],LED[1],LED[2],LED[3]... etc. 

 module fib( input clk, input reset_n, output LED, ); reg prev; reg actual; assign LED = actual; always @(posedge clk or negedge reset_n) begin if(!reset_n) begin prev <= 8'd0; actual <= 8'd1; end else begin prev <= actual; actual <= actual + prev; end endmodule   --- Quote End ---  

[Altera_Forum]

module fibclk(  

input clk,  input reset_n,  output [7:0] LED  );  reg [7:0] prev; reg [7:0] actual;  assign LED = actual;  always @(posedge clk or reset_n)  begin  if(!reset_n)   begin  prev = 8'd0;  actual = 8'd1;  end else   begin  prev = actual;  actual = actual + prev;  end  end endmodule  MAKE ATTENTION : 1) no edge on more than one signal in alway key (only the clock signal) !!!!! 2) <= is comparator in VERILOG but assignment in VHDL, you are in VERILOG so it is = affectation.  I don't understande your problem on the LED !!!  To see some think, you must use very low frequency clock, if not, you will see all LEDs ON !!!! You need to reduice the Frequency of the primary clock ( 0.5Hz is very good to see binary number of fabonacci). I prefer using 7seg dusplay.  Good luck  Impossible to contact you because my reply counter is too low (must be 10 to be able to send PM)