Single clock dual port ram issue

[Altera_Forum]

According the altera's ug, I can get the read out data from my dual port ram the next clock edge after the address valid. This show in the mega core's wave figure, pls check as attached file.  

    But the issue is that I got the read out data after 2 clock in fact, please check my signaltap jpg file. why?

[Altera_Forum]

It is correct. The address that was sampled by the memory on the first rising cycle that you highlighted is C1h. What the signaltap display is showing is that the address changed to CCh after the rising edge of the clock, will be read by the memory on the next clock cycle and will change the data bus to the correct value on the following clock cycle.

[Altera_Forum]

Hi, 

 You point it out, you are right. The sample clock and the address changing clock are the same clock, so when address changes, it is not valid, and the changed address is appear next clock.   thanks