Fitter Added Delay and False Paths

[Altera_Forum]

Hi All, 

 I have a design with a bank of configuration registers, that run to various state machines with different gated or muxed clocks. The reigster outputs are quasi-static, so I don't want to worry about synchronization. I have their output set as false path and my timing reports appear to ignore these paths. However when I look at my fitter report, under "Estimated Delay Added for Hold Timing Details" there is a lot of delay added from these configuration registers that have the false path. Is there any reason why the fitter would do this with the false path added? Any way to get a report of why the fitter added delay? Any other constraint it's meeting that the false path does not guarantee an exception to? Additionally I've been having some issues with minimum pulse widths that I can't get to go away with false paths, perhaps they are related.  Thanks in advance.

[Altera_Forum]

--- Quote Start ---  Hi All,  I have a design with a bank of configuration registers, that run to various state machines with different gated or muxed clocks. The reigster outputs are quasi-static, so I don't want to worry about synchronization. I have their output set as false path and my timing reports appear to ignore these paths. However when I look at my fitter report, under "Estimated Delay Added for Hold Timing Details" there is a lot of delay added from these configuration registers that have the false path. Is there any reason why the fitter would do this with the false path added? Any way to get a report of why the fitter added delay? Any other constraint it's meeting that the false path does not guarantee an exception to? Additionally I've been having some issues with minimum pulse widths that I can't get to go away with false paths, perhaps they are related.  Thanks in advance.  --- Quote End ---    If a path is made false then naturally the tool shouldn't attempt to care about tSU or tH at destination register of that path. The fact that you got hold delay added implies some other paths that are not included in false path constraint (possibly to same registers). This tH violation is common with gated clocks when clock delay becomes more than data delay and extra delay is added to data path.   The minimum pulse width duration has nothing to do with register timing window. It is a constraint by itself and again is common problem with gated clocks generated by user. It is as important as other violations and restricts fmax.

[Altera_Forum]

Are you sure the fiter is not adding delay to the *input* of those registers?