Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16644 Discussions

Fitter Error for fractional PLL

GD76
Novice
1,822 Views

The error in fitting is as follows. Going thorugh the knowledge base, not clear what the solution is.  It says "Location FRACTIONALPLL_X0_Y38_N0" already occupied. I can move to different location but not sure what constraint syntax is. Maybe others have seen the same issue.

 

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). 

Error (175001): The Fitter cannot place 1 fractional PLL, which is within PLL Intel FPGA IP CPU3000Qsys_pll.
Info (175028): The fractional PLL name(s): CPU3000Qsys:u0|CPU3000Qsys_pll:pll|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
Error (11239): Location FRACTIONALPLL_X0_Y38_N0 is already occupied by CPU3000Qsys:u0|CPU3000Qsys_ddr2:ddr2|CPU3000Qsys_ddr2_pll0:pll0|pll1~FRACTIONAL_PLL.
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

0 Kudos
1 Solution
sstrell
Honored Contributor III
1,809 Views

What device family and Quartus version and edition (Standard, Pro) are you using?

What IP are you using that might be conflicting with the use of a particular PLL?

Have you made I/O pin assignments that might be conflicting?

View solution in original post

0 Kudos
3 Replies
sstrell
Honored Contributor III
1,810 Views

What device family and Quartus version and edition (Standard, Pro) are you using?

What IP are you using that might be conflicting with the use of a particular PLL?

Have you made I/O pin assignments that might be conflicting?

0 Kudos
GD76
Novice
1,804 Views

Device is Cyclone V (5CEFA4F23C7). Quartus Standard version 18.1. There are no IO pin conflict looking thorough the QSF file (attached) The IPs are many DDR2 has pll and NIOS pll, pll reset monitor. 

0 Kudos
sstrell
Honored Contributor III
1,799 Views

It looks like you have incremental compilation enabled for the entire design, locking down the placement and routing.  That would prevent you from making a change like this.  Check the Design Partitions window.

0 Kudos
Reply