Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Fitter Report - Caret character - what does it mean?

Altera_Forum
Honored Contributor II
‎03-22-2016 02:18 PM
1,542 Views

Compiling for a C 5 SOC chip and in the fitter reports, "All package Pins" section, there is a '^' (caret) character that precedes signals. What does it mean? See below example: 

 

V4 36 3A ^DCLK Weak Pull Up -- On 402 

C1 437 9A ^GND -- -- -- 403 

F15 304 7A ^GND -- -- -- 404 

F17 295 7A ^GND -- -- -- 405 

G17 294 7A ^GND -- -- -- 406 

C16 306 7A ^HPS_CLK1 -- -- -- 407
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎03-22-2016 08:06 PM
877 Views

Maybe that's just how your text editor displays tabs?

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.