Fitter fails when placing ALTLVDS_RX instance on Arria V GX Starter Board

[Altera_Forum]

I am using the LVDS HSMC RX pins on the Arria V GX Starter Board, I have RX pins HSMA_RX_D[16:0] all to be clocked using HSMA_CLK_INP1 (all pins are LVDS). The incoming clock is 250MHz and the data is DDR but I need to have a deserialization factor of 4 (i.e. 125MHz output clock). I have tried to use the ALTLVDS_RX IP and regardless if I use an external PLL or have the PLL internal to the ALTLVDS_RX block I get an error during the fitting process after Analysis & Synthesis has succeeded: 

 Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PLL LVDS output(s)). Fix the errors described in the submessages, and then rerun the Fitter.  Error (175020): The Fitter cannot place logic PLL LVDS output that is part of Altera PLL pll_adc in region (169, 21) to (169, 24), to which it is constrained, because there are no valid locations in the region for logic of this type.  Info (14596): Information about the failing component(s):  Info (175028): The PLL LVDS output name(s): <PLL OUTPUT CLOCK AT DATA RATE>  Error (16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:  Error (180002): Can't place PLL LVDS output because the SERDES DPA is already driven by 2 clock and clock enable pairs (4 locations affected)  Info (175029): PLLLVDSOUTPUT_X169_Y21_N2  Info (175029): PLLLVDSOUTPUT_X169_Y22_N2  Info (175029): PLLLVDSOUTPUT_X169_Y23_N2  Info (175029): PLLLVDSOUTPUT_X169_Y24_N2  Info (175013): The PLL LVDS output is constrained to the region (169, 21) to (169, 24) due to related logic  Info (175015): The I/O pad HSMC_CLKIN_p[1] is constrained to the location PIN_AN3 due to: User Location Constraints (PIN_AN3)  Info (14709): The constrained I/O pad is contained within a pin, which drives a fractional PLL, which drives this PLL LVDS output  Some things I tried: 1) I looked at http://www.alteraforum.com/forum/archive/index.php/t-42882.html ... So I tried ALTLVDS_RX module to use the "Regional Clock" setting and the "Auto" clock output setting (before specifying the PLL was external when using an external PLL). 2) http://www.alteraforum.com/forum/showthread.php?t=46028 solved a similar issue using two different ALTLVDS_TX modules, I did the same except used one module for each input data pin 3) https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01032013_182.tablet.html mentioned using a buffer so I did that:   arriav_pll_lvds_output# (  .pll_loaden_enable_disable("true"),  .pll_lvdsclk_enable_disable("true"))  arriav_pll_lvds_output_inst (  .ccout({clkadc_rxen, clkadc_data}),  .loaden(lvds_clken),  .lvdsclk(lvds_clkdata)  );  lvds_adc rx_adc_lvds (  .rx_inclock(lvds_clkdata),  .rx_enable(lvds_clken),  .rx_in(HSMC_RX_p[14:2]),  .rx_out(adc_lvds_out[51:0])  );  I got the following error:  Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PLL LVDS output(s)). Error (175020): The Fitter cannot place logic PLL LVDS output in region (169, 21) to (169, 24), to which it is constrained, because there are no valid locations in the region for logic of this type.  Info (14596): Information about the failing component(s):  Info (175028): The PLL LVDS output name(s): arriav_pll_lvds_output_inst  Error (16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:  Error (180002): Can't place PLL LVDS output because the SERDES DPA is already driven by 2 clock and clock enable pairs (4 locations affected)  Am I doing something wrong? Is there something I am missing? Please note, if only one pin data pin is being clocked using the ALTLVDS_RX module it will work, my issue is it will not fit if I have multiple data pins (either using multiple ALTLVDS_RX blocks or using one multilple channel ALTLVDS_RX block)

[Altera_Forum]

I'm not sure of the real reason for the problem but you do realize that the fitter is complaining about an output not an input don't you? What has the output clock got to do with the Rx DPA?

[Altera_Forum]

--- Quote Start ---  I'm not sure of the real reason for the problem but you do realize that the fitter is complaining about an output not an input don't you? What has the output clock got to do with the Rx DPA?  --- Quote End ---    I assume they are referring to the output of the pll. It is the input to the RX DPA

[Altera_Forum]

UPDATE: I tried the same code on the Cyclone V GX Starter Kit and it works, of course the Cyclone V does not have DPA in the LVDS IP so that might be part of the reason. Does anyone have any idea how to get it to work on the Arria V? I am currently trying to work around the problem by using a PLL to generate a few phase shifted clocks and manually deserializing the data. This solution works for now but I suspect it will have setup and hold problems as the speeds change.

[Altera_Forum]

--- Quote Start ---  UPDATE: I tried the same code on the Cyclone V GX Starter Kit and it works, of course the Cyclone V does not have DPA in the LVDS IP so that might be part of the reason. Does anyone have any idea how to get it to work on the Arria V? I am currently trying to work around the problem by using a PLL to generate a few phase shifted clocks and manually deserializing the data. This solution works for now but I suspect it will have setup and hold problems as the speeds change.  --- Quote End ---    Hello Mark,  Did you get the solution for Arria V start board?   I am also having the same problem.  Can you share with me the way to deserialize the data?  Thanks for your help.  FYI: I am trying to deserialize LVDS o/p from TI ADC ADS4249.

[Altera_Forum]

--- Quote Start ---  Hello Mark,  Did you get the solution for Arria V start board?   I am also having the same problem.  Can you share with me the way to deserialize the data?  Thanks for your help.  FYI: I am trying to deserialize LVDS o/p from TI ADC ADS4249.  --- Quote End ---    Hi mghdallas, I'm no expert but this is what I did, if you spot errors or have other ideas please do share. My ADC was 500MSPS (I'm using the Intersil KAD5512P-50) so I wanted to deserialize by 4 because 500 and 250MHz seem too fast for the FPGA fabric (might need to move to Cyclone V going forward)  1) I used a PLL (not in LVDS mode) with a high bandwidth setting, it took the 250MHz reference clock from the ADC. Data is edge aligned. I have 2 output clocks from the PLL:  i - clkadc_045 - 125MHz (half the frequency) with a phase shift of 45 degrees  ii - clkadc_315 - 125MHz with a phase shift of 315 degrees.  2) Then I registered in the data on the positive and negative edges of each clock:  always @(posedge clkadc_315) begin  for (integer i = 0; i < ADCNBITS + 1; i = i + 1 ) begin : REG_LVDS0  adc_lvds_out[DESFACTOR*i + 0] <= adc_data_src;  end  end  always @(negedge clkadc_045) begin  for (integer i = 0; i < adcnbits + 1; i = i + 1 ) begin : reg_lvds1  adc_lvds_out[desfactor*i + 1] <= adc_data_src;  end  end  always @(negedge clkadc_315) begin  for (integer i = 0; i < ADCNBITS + 1; i = i + 1 ) begin : REG_LVDS2  adc_lvds_out[DESFACTOR*i + 2] <= adc_data_src;  end  end  always @(posedge clkadc_045) begin  for (integer i = 0; i < adcnbits + 1; i = i + 1 ) begin : reg_lvds3  adc_lvds_out[desfactor*i + 3] <= adc_data_src;  end  end  3) Then I register all the data one more time using clkadc_315 (I have an overrun bit as well as the ADC data and my data is inverted so ignore that stuff):  always @(posedge clkadc_315 or negedge adc_reset_n) begin  if (~adc_reset_n) begin  adc_or <= {DESFACTOR{1'b1}};  adc_data <= {(DESFACTOR*ADCNBITS){1'b1}};  end else begin  adc_or[DESFACTOR-1:0] <= ~adc_lvds_out[DESFACTOR*(ADCNBITS+1)-1:DESFACTOR*ADCNBITS];  adc_data[DESFACTOR*ADCNBITS-1:0] <= ~adc_lvds_out[DESFACTOR*ADCNBITS-1:0];  end  end  4) Then I added my timing constraints in the SDC file (input clock is half the clock frequency for me)  set lvds_data_tracemax 0.05  set lvds_data_tracemin 0  set lvds_clk_tracemax 0.05  set lvds_clk_tracemin 0  set lvds_tco_min -0.260  set lvds_tco_max 0.120  set lvds_maxdelay [expr $lvds_data_tracemax - $lvds_clk_tracemin + $lvds_tco_max]  set lvds_mindelay [expr $lvds_data_tracemin - $lvds_clk_tracemax + $lvds_tco_min]   create_clock -name clk_adc -period ${Tadcin}ns   # Rising edge constraints   set_input_delay -clock [get_clocks clk_adc] -max ${lvds_maxdelay}ns [get_ports HSMC_RX_p*]  set_input_delay -clock [get_clocks clk_adc] -min ${lvds_mindelay}ns [get_ports HSMC_RX_p*]   # Falling edge constraints  set_input_delay -clock [get_clocks clk_adc] -max ${lvds_maxdelay}ns [get_ports HSMC_RX_p*]   -add_delay -clock_fall  set_input_delay -clock [get_clocks clk_adc] -min ${lvds_mindelay}ns [get_ports HSMC_RX_p*]   -add_delay -clock_fall    # Mutlicycle Paths  # http://quartushelp.altera.com/14.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_set_multicycle_path.htm  set_multicycle_path -setup -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_045] 2  set_multicycle_path -hold -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_045] 1  set_multicycle_path -setup -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_315] 2  set_multicycle_path -hold -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_315] 1  6) I may have done my timing delays wrong because what ended up happening is the fitter inserted a delay from posedge clkadc_045 to the register so in the end the order was 3 0 1 2 instead of 0 1 2 3.    In your case, the ADC CLKOUT is center aligned with the data so you have other options. If you want to deserialize by 4, like I did, your phase shifts would be 0 and 90 degrees. Then register the data on the pos and neg edges of both of those. Alternatively, to deserialize by 2 you can just use the pos and neg edges of your incoming clock (or PLL with same frequency and 0 phase shift).