Fitter routing can't fit into device when we look the resource utilization is less than 60%. we are using stratix V device. how to fix this.

[kanthi]

Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error: Quartus Prime Fitter was unsuccessful. 2 errors, 30 warnings

Error: Peak virtual memory: 11292 megabytes

[Kenny_Tan]

may I know what is the Quartus version that you were using? What is the device that you were using? Can you attached your design.qar here to investigate.

Usually, the resource utilization will not be accurate as mention in 60% because the error pop out.

[kanthi]

Thanks for your reply : we are using Quartus version 15.1. The part no is s5phq_5sgxea7k2f40c2 (stratix V)

actually the setup slack was -2.7 for more than 1000 path.

due to setup slack our design is not functionally correct.

so we changed the advance setting option for synthesis and fitter in setting window(compiler setting)

after that we got this error msg:

thanks

[Kenny_Tan]

Got it, -2.7 is very huge slack even if you want to change a different setting options to close the timing for 1000path.

And it will be quite common that you will hit error message of no route because you put the fitting engine to more load.

What I would suggest is look into your design failure in the timing analyzer. Start analyze those failing path before do any setting changes. Sometimes, some of the path would be repeating failure for for a bus that can be solve easily, by pipeliping and etc.

[kanthi]

Hi KTan, I need you great help to fix the negative slack, In our design we are using BRAM. the MM_inter connectivity taking lot of space. and avalon streaming too. can we directly access BRAM without MM_interconnection? if so please advice how to do it. The Qsys automatically insert avalon streaming. (adapter).can we remove manually and connect directly(without avalon streaming) in this case we will get some routing area to the fitter. please advice thanks sivakumar

[Kenny_Tan]

Did see the failure in the platform designer interconnect? If yes, there are 3 ways to solve it

1) in qsys -> press system -> show system with interconnect -> memory mapped interconnect -> manually add register there

2) in your qsys, add pipeline register module

3) go to interconnect requirement-> limit interconnect requirement -> increase it

Qsys automatic add adapter when there are mismatch btw the avalon. You cannot simply remove those adapter as it will cause your function to be broken. Thanks

[Kenny_Tan]

any update?

[kanthi]

Hi KTan, Thank you very much for your guidance. Sorry for the delay update. Now there is no slack factor on MM_interconnection alternatively, the slack factor move in to other modules. our utilization is less than 66% of resource. even though we are getting high slack factor is any other way to remove this? we can able to achieves if we disabled the BRAM (on chip memory). is any alternate method for BRAM replacement info: Family Stratix V Device 5SGXEA7K2F40C2 Timing Models Final Logic utilization (in ALMs) N/A Total registers 222223 Total pins 548 Total virtual pins 452 Total block memory bits 34,836,496 Total DSP Blocks 70 Total HSSI STD RX PCSs 9 Total HSSI 10G RX PCSs 2 Total HSSI GEN3 RX PCSs 9 Total HSSI PMA RX Deserializers 10 Total HSSI STD TX PCSs 9 Total HSSI 10G TX PCSs 2 Total HSSI GEN3 TX PCSs 9 Total HSSI PMA TX Serializers 11 Total HSSI PIPE GEN1_2s 9 Total HSSI GEN3s 9 Total PLLs 19 Total DLLs 2 Thanks KTan,

[Kenny_Tan]

Bram will be running very slow, can you use M20k?

How do you use the ram? by calling out the IP or by coding?

If by using the IP, there should be an option for you to change it. If you are using coding, you can force it to use M20 using attribute.

Also, after you use M20k, make sure the register are tied inside the ram so that the performance will get better. You can check whether the register is pack to the ram in the syntheis/fitter reports.

[kanthi]

hi KTan, Thanks, we will try and let you know the result. here with i am enclosed our constraints file top.sdc -- please advice any changes or additional setup is require do you have any recommended setting for synthesis and fitting? when i do the design partition, some time the logic region is small in size (20% higher value we set from estimated size ). i adjusted the area then do the fitter (place and route). it is start from synthesis again. in general , we didn't change anything on the design level. already the synthesis and elaboration done. The Quartus tools start from the very beginning. it is taking more than for full compilation (more than 6 to 8 hr). is any other way to do only fitter(when i change only on design partition - "area size changes") so, we can save some time. thanks Mr. Ktan

[kanthi]

Hi Mr.KTan How to fix this warning Warning (177007): PLL(s) placed in location FRACTIONALPLL_X98_Y11_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Info (177008): PLL mango_demo:mango_demo_0|mango_demo_bw_ddr3_system:bw_ddr3_system|mango_demo_bw_ddr3_system_bw_ddr3_mst:bw_ddr3_mst|mango_demo_bw_ddr3_system_bw_ddr3_mst_emif_0:emif_0|mango_demo_bw_ddr3_system_bw_ddr3_mst_emif_0_pll0:pll0|pll1~FRACTIONAL_PLL Warning (177007): PLL(s) placed in location FRACTIONALPLL_X98_Y109_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Info (177008): PLL mango_demo:mango_demo_0|mango_demo_bw_qdr2_system_0:bw_qdr2_system_0|mango_demo_bw_qdr2_system_0_qdra:qdra|mango_demo_bw_qdr2_system_0_qdra_qdr_0:qdr_0|mango_demo_bw_qdr2_system_0_qdra_qdr_0_pll0:pll0|pll1~FRACTIONAL_PLL Warning (177007): PLL(s) placed in location FRACTIONALPLL_X210_Y53_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks I set the value in assignment editior mango_demo:mango_demo_0|mango_demo_bw_qdr2_system_0:bw_qdr2_system_0|mango_demo_bw_qdr2_system_0_qdra:qdra|mango_demo_bw_qdr2_system_0_qdra_qdr_0:qdr_0|mango_demo_bw_qdr2_system_0_qdra_qdr_0_pll0:pll0|pll1~FRACTIONAL_PLL PLL compensate direct when i synthesis it was ignored thanks

[Kenny_Tan]

1) Can you post the warning question to another thread? We will try to sort this timing problem first.

2) Can you attached your design.qar here?With the design.qar, I can look into the bram stuff.

[kanthi]

hi Ktan, you mean the archives files(include fpga_binaries and sub folder " output and synthesis file) the file size is very big close to 2 GB if you mean different design.qar mean please let me know where it will be locate in the project environment Thanks sivakumar

[Kenny_Tan]

Hi,

When you press project -> archieve project. It will become a *.qar file format.

Usually, it will only include the source files. If you include the output synthesis file, you can manually exclude it out there.

If it still exceed 2Gb, let me know. Also, make sure that your project are fine to attached over here as it is in public. Let me know if you want to send it not in public format.

Thanks

[kanthi]

Hi KTan, Sorry for the delay reply. in india long holidays. i will back to office by Thursday. yes, we can't send it in public format thanks with best regards sivakumar

[Kenny_Tan]

Hi Sivakumar,

Since you can't send the design in public. Can you provide us the email address?

Thanks,

[kanthi]

hi KTan, mail ID is sivakumar@axlware.com thanks you

[Kenny_Tan]

Thanks, you can check your inbox.

[Kenny_Tan]

Just to remind you to check your inbox again.

[kanthi]

Hi KTan, Thanks you very much for your great support. For our application, two parallel path one is MDI and other one is OOI. current we are Enabled only MDI path. (disabled OOI). if we enable OOI path then we facing this fitting issue. Time being we are focus only on MDI path.so, we can close this issue for while. i will rise the ticket again once we are completed the MDI path and back to OOI. once again thanks for your Great support and Tracking Great KTan, with best regards sivakumar