Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 30 warnings
Error: Peak virtual memory: 11292 megabytes
may I know what is the Quartus version that you were using? What is the device that you were using? Can you attached your design.qar here to investigate.
Usually, the resource utilization will not be accurate as mention in 60% because the error pop out.
Thanks for your reply : we are using Quartus version 15.1. The part no is s5phq_5sgxea7k2f40c2 (stratix V)
actually the setup slack was -2.7 for more than 1000 path.
due to setup slack our design is not functionally correct.
so we changed the advance setting option for synthesis and fitter in setting window(compiler setting)
after that we got this error msg:
Got it, -2.7 is very huge slack even if you want to change a different setting options to close the timing for 1000path.
And it will be quite common that you will hit error message of no route because you put the fitting engine to more load.
What I would suggest is look into your design failure in the timing analyzer. Start analyze those failing path before do any setting changes. Sometimes, some of the path would be repeating failure for for a bus that can be solve easily, by pipeliping and etc.
Did see the failure in the platform designer interconnect? If yes, there are 3 ways to solve it
1) in qsys -> press system -> show system with interconnect -> memory mapped interconnect -> manually add register there
2) in your qsys, add pipeline register module
3) go to interconnect requirement-> limit interconnect requirement -> increase it
Qsys automatic add adapter when there are mismatch btw the avalon. You cannot simply remove those adapter as it will cause your function to be broken. Thanks
Bram will be running very slow, can you use M20k?
How do you use the ram? by calling out the IP or by coding?
If by using the IP, there should be an option for you to change it. If you are using coding, you can force it to use M20 using attribute.
Also, after you use M20k, make sure the register are tied inside the ram so that the performance will get better. You can check whether the register is pack to the ram in the syntheis/fitter reports.
1) Can you post the warning question to another thread? We will try to sort this timing problem first.
2) Can you attached your design.qar here?With the design.qar, I can look into the bram stuff.
When you press project -> archieve project. It will become a *.qar file format.
Usually, it will only include the source files. If you include the output synthesis file, you can manually exclude it out there.
If it still exceed 2Gb, let me know. Also, make sure that your project are fine to attached over here as it is in public. Let me know if you want to send it not in public format.