Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Fitter routing operation verbosity

AEsqu
Novice
782 Views

Hello,

Vivado brings several information while the routing is running (congestion level,  TNS/WNS, ..)

which are quite useful.

Quartus stays totally quite and do not show any info,

only when it finishes (with an error if it cannot route for example).

Is it possible to raise the verbosity to get some information of what quartus is busy with?

I use quartus prime 21.1.0 standard edition.

 

 

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AEsqu
Novice
769 Views

Well, when it fails it gives the signal names it couldn't route at the end + the coordinates.

 

 

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SyafieqS
Moderator
725 Views

Hi Alexandre,


You can find more information in compilation report regarding the routing. Judging from your snapshot, failed routing is due to resource used more that device capacity, you probably need to modify your code or do some optimization to reduce the resource. 


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SyafieqS
Moderator
712 Views

Hi Alexandre,


May I know if there is any update from your end?


Regarding the info related to TNS,WNS, you can actually look at timing analyzer report in compilation report (assuming successfully pass the flow) with simplify information. You can see more details in Timing Analyzer for more other report.


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AEsqu
Novice
697 Views

Ok so you confirm that verbosity cannot be changed during the run.

Let's close the ticket.

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SyafieqS
Moderator
702 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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AEsqu
Novice
681 Views

Note: For some reason, using fast fit makes it easier to route than auto fit.

 

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AEsqu
Novice
651 Views

What does really help Quartus to route the design is to reduce the fanout.

For example a fanout of 128 set in Synplify helps a lot.

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aesq
Novice
303 Views

I will try the same option as I indicated in the other topic to solve the routing problem in the cyclone V:

set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION OFF

 

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