Floating Point and Fixed Point.

[Altera_Forum]

I am beginner in VHDL code. I am currently using Quartus II and wonder if anyone can recommend a good and easy-to-use floating point library? I know there is a megafunction from altera. But, I just want to know what is the latest free library? Is it from IEEE by David Bishop?  

 Also, how to compile a new package/library in Quartus II as I am trying to include the ieee floating point library in Quartus II.    Thx very much....

[Altera_Forum]

I wouldnt recommend using the new IEEE floating point library just yet - you're unlikely to get any pipelining in the functions. A single floating point add takes several clock cycles to run at a decent speed, and a divide/square root takes tens of clock cycles to complete at a decent speed. The IEEE functions will all complete in a single clock cycle, so you will not get a decent FMax out of them. 

 Stick with the altera FP library for now - it is the most optimised for altera products anyway. You dont have to use the mega function, just add the lines:  LIBRARY altera_mf;  USE altera_mf.altera_mf_components.all;   to the top of your design, and you can call in components manually from the library. If you go to help->megafunctions LPM, it will tell you the use of all the ports and generics.  On the other hand, the IEEE fixed point library is a godsend. No more scrabbling around with unsigned and signed types.

[Altera_Forum]

Thanks for your information. Do you have a simple example, say, using the FP library to add two floating point values? Thank you very much!

[Altera_Forum]

signal a : std_logic_vector(31 downto 0); signal b : std_logic_vector(31 downto 0); signal r : std_logic_vector(31 downto 0); begin fp_add : altfp_add_sub generic map ( DIRECTION => "ADD", ROUNDING => "TO_NEAREST", width_exp => 8, width_man => 23, pipeline => 11 ) port map ( aclr => reset, clock => clk, dataa => a, datab => b, result => r ); The above example uses default values for exponent and mantissa width, of 8 and 23, and has an 11 clock cycle latency by default.

[Altera_Forum]

Thank you so much. Would you mind to provide the whole code which I can compile it directly? Sorry for the stupid request as I am really new and I would like to learn from example. Thank you so so much!

[Altera_Forum]

you can also try altfp_add_sub in the MegaWizard.

[Altera_Forum]

I wrote an example myself as below. I think it is the correct way to do a summation for floating point values. Am I right? 

 Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Library altera_mf; use altera_mf.altera_mf_components.all;  entity floatadd is port(  inA,inB : in std_logic_vector(31 downto 0);  inclk : in std_logic;  out1 : out std_logic_vector(31 downto 0) ); end floatadd;  architecture add of floatadd is  component altfp_add_sub  generic (  direction : string := "ADD";  pipeline : natural := 11;  rounding : string := "TO_NEAREST";  width_exp : natural := 8;  width_man : natural := 23  );  port(  clock : in std_logic;  dataa : in std_logic_vector(width_exp+width_man+1-1 downto 0);  datab : in std_logic_vector(width_exp+width_man+1-1 downto 0);  result : out std_logic_vector(width_exp+width_man+1-1 downto 0)  ); end component;  begin  G1: altfp_add_sub  port map (inclk,inA,inB,out1); end add;

[Altera_Forum]

The best thing to do is try synthesising it. 

 But I know its not going to work.  First, you dont need the compoenent declaration in your file - its already in the altera_mf_components package you included. If you kept this component here, it wouldnt be able to compile because it wont be able to find a matchin entity instantiation (unless you generated it from the mega-wizard, but if it was a megawizard generated component, it would be called altfp_add_sub).   You need to either use the megawizard then copy/paste the component declaration from the file created, then your G1 instance will work, otherwise get rid of the component in your file and do named association on the port map, instead of positional. Use the altera help for information on port names and such.

[Altera_Forum]

Thank you so much for your comments. I have modified it as follows: 

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Library altera_mf; use altera_mf.altera_mf_components.all;  entity floatadd is port(  inA,inB : in std_logic_vector(31 downto 0);  inclk : in std_logic;  out1 : out std_logic_vector(31 downto 0) ); end floatadd;  architecture add of floatadd is begin fp_add : altfp_add_sub  generic map (  DIRECTION => "ADD",  ROUNDING => "TO_NEAREST",  width_exp => 8,  width_man => 23,  pipeline => 11  )  port map (  clock => inclk,  dataa => inA,  datab => inB,  result => out1  ); end add;   I tried to compile it and it is working. Have to simulate it and check with the results. But is this make senses to you?

[Altera_Forum]

Hi, I was looking for a code in VHDL that could realize the basic operations (+ - * /). 

I tried to use libraries, altera megapack, but always something goes wrong.  I am having the same error with simulation in a lot of programs: "Error: Specify valid fractional value for signal "A" from -1.0 to 9.9999999953433871e-001 with multiple value of 4.6566128730773926e-010." The code user cwjcwjcwj post, is taking me to the same error, I'm probably doing something wrong.  If someone could help me, I really appreciate!  Thank's!