For Loop Complexity

[Altera_Forum]

I would like to know if the larger 'for' loops are spilt into a number of smaller for loops will that reduce the complexity and resource utilized. Does the function and module concept consumes the same resource.  

 example: for(k=0;k<652;k=k+1) begin F=F+(u[x]*v[y]); end  This loop will be repeated for about 160 times. Kindly explain about this

[Altera_Forum]

Let me explain my view and experience with for loops. discussion relates to vhdl and I hope it applies to verilog or other HDL. 

 when you declare for loop then you are asking the compiler to insert the statements for you(to unroll sequentially). The compiler will do that at compile time and the hardware got nothing to do with the loop from that point on.   for example   for i in 0 to 7 loop  a(i) <= '1'; end loop;   the compiler will unroll the loop into: a(0) <= '1'; a(1) <= '1'; .... a(7) <= '1';   thats all, thus if instead say: for i in 0 to 7 loop  a <= '1'; end loop;   the compiler will unroll the loop into: a <= '1'; a <= '1'; .... a <= '1'; which is meaningless and only last assignment is taken to hardware.

[Altera_Forum]

Cause a HDL iteration scheme is completely executed at compile time and the resulting logic handed over to the usual optimizing process, the resource utilization doesn't depend on the particular coding style, as long as the logic function is unchanged. 

 To estimate the possible complexity, you should consider meaningful examples. your below example isn't, cause the same expression is added 652 times (x an y are constant during iteration). for(k=0;k<652;k=k+1) begin F=F+(u*v); endThe synthesis problem with this particular example isn't the iteration, but the indexing. It forces inference of multiplexers. Depending on the x/y range and u/v bit size, it may already go beyond the logic cell and routing resources of a medium size FPGA. With x and y varying during the iteration, it's most likely unsynthesizable.  I assume, that the code has been written by someone, who didn't yet understand the meaning of iteration schemes in HDL.