Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
The Intel sign-in experience is changing in February to support enhanced security controls. If you sign in, click here for more information.
15812 Discussions

For the instantiation of ddr3, when compiling to the fitter step, an error error occurs: 14566.

Ryan-SEU
Novice
235 Views

In my PCB design, I usedcyclone V series FPGA and two pieces of Micron DDR3 SDRAM. I completed the parameter configuration of the IP core according to the guidelines , but when I was instantiating, when I ran to the step of the fitter, the following error occurred:
-------------------------------------------------------------------------------------------------------------
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 DLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic DLL that is part of DDR3 SDRAM Controller with UniPHY Intel FPGA IP ddr3_x32 in region (3, 0) to (3, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The DLL name(s): ddr3_x32:ddr3_wr_buffer_test|ddr3_x32_0002:ddr3_x32_inst|altera_mem_if_dll_cyclonev:dll0|dll_wys_m
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175013): The DLL is constrained to the region (3, 0) to (3, 0) due to related logic
Info (175015): The I/O pad FPGA_CLK1_REF40MHz is constrained to the location PIN_Y15 due to: User Location Constraints (PIN_Y15)
Info (14709): The constrained I/O pad drives a fractional PLL, which drives this DLL
Error (175006): Could not find path between the DLL and destination DQS Group
Info (175027): Destination: DQS Group fed by DQS I/O pad DDR3_DQS[0]
Info (175013): The pin is constrained to the region (6, 115) to (112, 115) due to related logic
Info (175015): The I/O pad DDR3_DQ[1] is constrained to the location PIN_D22 due to: User Location Constraints (PIN_D22)
Info (14709): The constrained I/O pad is contained within a pin, which is contained within this DQS Group
Error (175022): The DLL could not be placed in any location to satisfy its connectivity requirements
Info (175021): The DQS Group was placed in location DQS Group containing D25
Info (175029): 1 location affected
Info (175029): DLL_X3_Y0_N0
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 7 errors, 8 warnings
Error: Peak virtual memory: 5963 megabytes
Error: Processing ended: Mon Apr 04 15:03:26 2022
Error: Elapsed time: 00:00:37
Error: Total CPU time (on all processors): 00:00:37

-------------------------------------------------------------------------------------------------------------

I didn't find the cause of the problem and the solution.
Attach my quartus project.

0 Kudos
1 Solution
Ryan-SEU
Novice
190 Views

Hi Adzim,

Thank you for your reply!

I have solved this problem. The reason is that the PLL reference clock used for the first time cannot be routed to the bank where the DDR3 is located, so quartus prompts me with the above error message. When I changed another reference clock, the problem went away.

 

Ryan-SEU

View solution in original post

5 Replies
sstrell
Honored Contributor III
214 Views

As the error states, your placement selections are preventing the placement of a DLL for the memory interface.

When placing the pins in the Pin Planner, did you enable the DQ/DQS view to see the valid locations to place the DQ/DQS pins?  Did you run the .tcl script that is created when you generate the IP (I think it's called pin_assignments.tcl)?

Ryan-SEU
Novice
190 Views

Hi sstrell,

Thank you for your reply!

I have solved this problem. The reason is that the PLL reference clock used for the first time cannot be routed to the bank where the DDR3 is located, so quartus prompts me with the above error message. When I changed another reference clock, the problem went away.

 

Ryan-SEU

AdzimZM_Intel
Employee
198 Views

Hi Ryan-SEU,


May I know the Quartus version that you're working on?


Thanks,

Adzim


Ryan-SEU
Novice
191 Views

Hi Adzim,

Thank you for your reply!

I have solved this problem. The reason is that the PLL reference clock used for the first time cannot be routed to the bank where the DDR3 is located, so quartus prompts me with the above error message. When I changed another reference clock, the problem went away.

 

Ryan-SEU

AdzimZM_Intel
Employee
180 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Reply