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Altera_Forum
Honored Contributor I
1,454 Views

Fully Synthesizable Fix Point package

Hi, 

Great- I'v just learned how to use fully synthesizable floating point arithmetic calculation (using MegaFunction/IP cores). Now, how can I implement fully synthesizable Fix point calculation? I couldn't find any MegaFunction/ IP cores for that purpose… 

Thanks a lot, 

Idan
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5 Replies
Altera_Forum
Honored Contributor I
85 Views

Fixed point aritmetic is just integer arithmetic, offset by 2^n. So no special IP is needed.

Altera_Forum
Honored Contributor I
85 Views

H; 

Thanks alot for your quick response! 

Where can I find an example for this kind of code? 

Thanks againe...  

Idan
Altera_Forum
Honored Contributor I
85 Views

in VHDL - its simple, especially if you use the fixed point package: 

 

use ieee.fixed_pkg.all; .... signal a : sfixed(7 downto -8); -- 1 sign bit, 7 integer bits, 8 fraction bits - ie. integer offset by 2^8 signal b : sfixed(15 downto -16); ... b <= a*a;  

 

this can all be done with the numeric_std package, but you need to keep track of the offset yourself.
Altera_Forum
Honored Contributor I
85 Views

Does the "fixed_pkg" is fully synthesizable?

Altera_Forum
Honored Contributor I
85 Views

 

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Does the "fixed_pkg" is fully synthesizable? 

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Yes. While full support only comes with Quartus Pro 16.0, you can use the '93 compatible version for compilation. 

Otherwise all of this can be done with numeric_std, which is compatible with all versions of quartus.
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