Hi everyone.I am writing a code in OpenCL for a Stratix V FPGA and the return value for the CL_DEVICE_MAX_CLOCK_FREQUENCY is 1Ghz. Is there any way to increase the clock speed? Also is this value the actual clock value used to run the kernel in the FPGA? Thanks
That value shows nothing; the actual operating frequency will be determined after placement and routing of the kernel and is generally in the range of 150-300 MHz.
Clock speed is set in the BSP. The clock speed your design will run at is in the reports generated by aoc. If for some reason your kernel can't run at the speed set by the BSP, aoc will compile it to run slower. This info would be included in the aoc-generated reports.