GBX + pin assignment

[Altera_Forum]

Hi all, 

 There is something that I don't understand. I am trying to set up a PCIe x1 Core inside a Cyclone IV GX15 device (not a development board but my own design), with the Hard IP compiler and QSys.  My problem is during pin assignment. I see there is an ALTGX block inside the PCIe core, so this should be enough to tell Quartus that I am going to use a transceiver. So I assign 1.5-V PCML I/O standard to the positive side of the differential pair of the transceiver pin (E2/E1 for RX and C2/C1 for TX, that is the second GXB, there is nothing on the first GXB) but when I try an I/O assignment analysis if fails on :  Error (167038): Channel 0 transceiver atom "PCIe_TX" cannot be placed on the transceiver block channel 1 at location PIN_C2 Error (167038): Channel 0 transceiver atom "PCIe_RX" cannot be placed on the transceiver block channel 1 at location PIN_E2 Error (167038): Channel 0 transceiver atom "PCIe_TX(n)" cannot be placed on the transceiver block channel 1 at location PIN_C1 Error (167038): Channel 0 transceiver atom "PCIe_RX(n)" cannot be placed on the transceiver block channel 1 at location PIN_E1    Where did I make my mistake ? or is there something stupid like "if you use a GXB, start with number one !".   Thanks for your help,  Erik.

[Altera_Forum]

Can I then maybe just ask someone to point me to the right document ? (I read tens so far, with no success) 

 Erik.

[Altera_Forum]

Hi Erik, 

  --- Quote Start ---  Can I then maybe just ask someone to point me to the right document?   --- Quote End ---    There's a few example designs in this thread here:  http://www.alteraforum.com/forum/showthread.php?t=35678  Try building one of them, and then editing the design to match the pin assignments on your custom board.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 This is very useful. I will try. I saw there is a good documentation with it, I should be able to implement all this without any problems now. thanks for sharing  All the best,  Erik.