Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16916 Discussions

GND connection restriction between Logic Lock regions

esantana
Beginner
363 Views

Hello,

I am trying to realise a design with 3 logic regions (using logic lock). All of them are reserved regions (no connections between them). 

However, it is a conection outside the regions. It is the GND and it enters all reserved regions. I attach an image of the regions and the GND connection. 

esantana_0-1731917798971.png

Is it possible to restrict the GND connection? I would prefer each region to have its own GND connection and not a shared GND outside the regions.

 

Thanks in advance

 

Labels (1)
0 Kudos
7 Replies
FvM
Honored Contributor I
358 Views

Hi,
what does it mean? Is GND the name of a logic signal in your design? If it refers to logic 0, it doesn't involve actual connections.

0 Kudos
esantana
Beginner
341 Views

Hi @FvM,

 

It is not the name of a logic signal.

This signal "GND" is the "0" value that is loaded into different counters when their clear input is activated in normal operation (by different output signals from state machines, for example).

The content of the cell that drives this "GND" is shown in this image:

esantana_0-1731920566253.jpeg

And the content of a destination cell is shown in this image:

esantana_2-1731921315835.png

 

What do you mean by "If it refers to logic 0, it doesn't involve actual connections"? Is it just a representation?

 

Thanks

 

0 Kudos
FvM
Honored Contributor I
328 Views

O.k. GND is no signal and doesn't need any routing  between regions. I guess you see a tool bug.

0 Kudos
sstrell
Honored Contributor III
258 Views

Can you show some code that shows this implementation?  Logic 0 does not need to route to a specific location on the device unless you've added some code that would define it.  You say "GND" is not defined as a signal, but the Chip Planner screenshot you show says otherwise unless there is some other logic you've defined that is causing this issue.

0 Kudos
Kenny_Tan
Moderator
199 Views

Hi,


Can you attached your design so that I can take a look into the issues?


If you think you need to send to Intel privately, do let me know.


Thansk,

Best regards,

Kenny Tan


0 Kudos
Kenny_Tan
Moderator
165 Views

not sure if you have any update?


0 Kudos
Kenny_Tan
Moderator
71 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



0 Kudos
Reply