GND connection restriction between Logic Lock regions

[esantana]

Hello,

I am trying to realise a design with 3 logic regions (using logic lock). All of them are reserved regions (no connections between them). 

However, it is a conection outside the regions. It is the GND and it enters all reserved regions. I attach an image of the regions and the GND connection. 

Is it possible to restrict the GND connection? I would prefer each region to have its own GND connection and not a shared GND outside the regions.

Thanks in advance

[FvM]

Hi,
what does it mean? Is GND the name of a logic signal in your design? If it refers to logic 0, it doesn't involve actual connections.

[esantana]

Hi @FvM,

It is not the name of a logic signal.

This signal "GND" is the "0" value that is loaded into different counters when their clear input is activated in normal operation (by different output signals from state machines, for example).

The content of the cell that drives this "GND" is shown in this image:

And the content of a destination cell is shown in this image:

What do you mean by "If it refers to logic 0, it doesn't involve actual connections"? Is it just a representation?

Thanks

[FvM]

O.k. GND is no signal and doesn't need any routing  between regions. I guess you see a tool bug.

[sstrell]

Can you show some code that shows this implementation?  Logic 0 does not need to route to a specific location on the device unless you've added some code that would define it.  You say "GND" is not defined as a signal, but the Chip Planner screenshot you show says otherwise unless there is some other logic you've defined that is causing this issue.

[KennyTan_Altera]

Hi,

Can you attached your design so that I can take a look into the issues?

If you think you need to send to Intel privately, do let me know.

Thansk,

Best regards,

Kenny Tan

[KennyTan_Altera]

not sure if you have any update?

[KennyTan_Altera]

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