Gate Level Netlist

[Altera_Forum]

Let's say that you have a hierarchical design with the Top Level file (call it topLevel.vhd) instantiating various modules such as modA.vhd, modB.vhd, modC.vhd, and so on. Is their a way to have Quartus write the gate level netlist of only say modB.vhd rather than writing the whole gate level netlist for topLevel.vhd? This is just a question regarding runnign the timing netlist in my functional simulation in Aldec for a specific module. Thanks. James

[Altera_Forum]

It doesn't seem that quartus_eda - the utility that dumps netlists - has a parameter to specify a top-level instance. 

The closest option to what you're asking is "--vcd_tb_design_instance_name". But the output is a VCD file, not RTL.  It might also not be possible to do it at all. For example when generating flat netlists with this option: "--maintain_design_hierarchy=off". Then an instance-specific netlist looses its meaning.  Thanks, Evgeni

[Altera_Forum]

Why do you want to see only modB.vhd? Does it take too long for Quartus to generate the whole gate level netlist? 

 What about commenting out modA and modC?

[Altera_Forum]

just make modB the top level file and generate that?

[Altera_Forum]

--- Quote Start ---  just make modB the top level file and generate that?  --- Quote End ---    That could conceivably work as long as Quartus would synthesize it, and you don't mind the effort of creating yet another Quartus project for just one module. That was part of the motivation in the first place.

[Altera_Forum]

I only want to see a specific module to check timing on that module; because it is the one that is suspect, and simulating the entire design is cumbersome and takes significant time.

[Altera_Forum]

--- Quote Start ---  I only want to see a specific module to check timing on that module; because it is the one that is suspect, and simulating the entire design is cumbersome and takes significant time.  --- Quote End ---    You either trust the tool or not. You don't need to check part of design for timing when you can check all design. TQ will let you know if it passed or not assuming any multicycle paths are correct. Freezer may help or build variation etc. In most cases it turns out to be user logic error.

[Altera_Forum]

--- Quote Start ---  You either trust the tool or not. You don't need to check part of design for timing when you can check all design. TQ will let you know if it passed or not assuming any multicycle paths are correct. Freezer may help or build variation etc. In most cases it turns out to be user logic error.  --- Quote End ---    That sounds like a judgment based on design philosophy, not a specific request for the tool to do something.