Gate level simulation fail?

[Altera_Forum]

Hey guys, 

 I'm trying to measure the dynamic/static power dissipated in my design which contains floating point adders and multipliers. For that I try to run the gate level simulation, write out the VCD file and use that as input to my PowerPlay Power Analyzer for accurate power estimation. Problem occurs when I try to step the clock frequency starting from 10MHz up to fmax, in increments of 10MHz.  For example, after synthesizing and fitting, TimeQuest reports fmax close to 200MHz with no setup and hold violations. When I run gate level simulation I can increase my clock frequency up to 80MHz. If I try to clock my design at 90MHz, the gate level simulation will fail setup/hold timing violations. I can see a lot of errors in the console window in ModelSim-Altera, with lots of red Xs in the waveform window.  How come I can't clock my design as fast as TimeQuest says I can in gate level simulation?  For completeness, here's my sdc file:  create_clock -period 5.50 -name clock [get_ports {clock}] derive_pll_clocks set_clock_uncertainty -from { clock } -to { clock } -setup 0.01 set_clock_uncertainty -from { clock } -to { clock } -hold 0.01 set_false_path -from [get_ports {aclr}] set_output_delay -clock { clock } 0.01 [get_ports {out* h*}] set_input_delay -clock { clock } 0.01 [get_ports {in*}]

[Altera_Forum]

--- Quote Start ---  Hey guys,  I'm trying to measure the dynamic/static power dissipated in my design which contains floating point adders and multipliers. For that I try to run the gate level simulation, write out the VCD file and use that as input to my PowerPlay Power Analyzer for accurate power estimation. Problem occurs when I try to step the clock frequency starting from 10MHz up to fmax, in increments of 10MHz.  For example, after synthesizing and fitting, TimeQuest reports fmax close to 200MHz with no setup and hold violations. When I run gate level simulation I can increase my clock frequency up to 80MHz. If I try to clock my design at 90MHz, the gate level simulation will fail setup/hold timing violations. I can see a lot of errors in the console window in ModelSim-Altera, with lots of red Xs in the waveform window.  How come I can't clock my design as fast as TimeQuest says I can in gate level simulation?  For completeness, here's my sdc file:  create_clock -period 5.50 -name clock [get_ports {clock}] derive_pll_clocks set_clock_uncertainty -from { clock } -to { clock } -setup 0.01 set_clock_uncertainty -from { clock } -to { clock } -hold 0.01 set_false_path -from [get_ports {aclr}] set_output_delay -clock { clock } 0.01 [get_ports {out* h*}] set_input_delay -clock { clock } 0.01 [get_ports {in*}]  --- Quote End ---    Hi,  when do the timing violations occur ? At the beginning of the simulation ? During the reset phase ? Are the violation input signal related ?  kind regards  GPK

[Altera_Forum]

Hi GPK, 

 The timing violations is only at the beginning of the simulation. Since then, I have optimized my design and the timing violations no longer occurs.   I have another question, however. Is it possible to force fmax on the design? I have tried to Change my fitter effort under Settings > Fitter Settings > Fitter Effort from Standard Fit to Auto Fit (reduce fitter effort after meeting timing requirement). If in my SDC file, I specific a clock of 20MHz, I still sees a fmax of 200 some MHz.  Is there a way to change the settings so that Fmax of the design reflects what I have specified in SDC file?  Regards Danny

[Altera_Forum]

--- Quote Start ---  Hi GPK,  The timing violations is only at the beginning of the simulation. Since then, I have optimized my design and the timing violations no longer occurs.   I have another question, however. Is it possible to force fmax on the design? I have tried to Change my fitter effort under Settings > Fitter Settings > Fitter Effort from Standard Fit to Auto Fit (reduce fitter effort after meeting timing requirement). If in my SDC file, I specific a clock of 20MHz, I still sees a fmax of 200 some MHz.  Is there a way to change the settings so that Fmax of the design reflects what I have specified in SDC file?  Regards Danny  --- Quote End ---    Hi Danny,  if you want to reduce the compile time more you can try the setting "Fast fit"., but it lookslike that your design could be very easily implement in the FPGA. The higher fmax indicates that you have a lot of margin in your design. You could choose e.g. a much slower speedgrade of the FPGA or your could do more processing during a clock cycle.  Kind regards  GPK