Gate level simulation problem in Modelsim while using Verilog output for Cyclone

[Altera_Forum]

I am using Cyclone IV E, ModelSim 6.6d and Quartus 11.0. 

I am using Verilog output format for the netlist writer. Modelsim opens correctly for RTL simulation but for gate level simulation there are errors "including" some library files. Each time these libraries need to be manually added. Is there a workaround?

[Altera_Forum]

Add -L cycloneiv_ver -L altera_ver to your vsim command.