Gatel level sim not same as RTL

[Altera_Forum]

Hi, I'm having some issues with my gate level sim not matching my RTL. I need a gate level sim to gather some toggle rates for power estimation.  

 The gate level netlist (.vho) is generated from Altera Quartus II software and I plug in the gate level netlist in place of the DUT and keep the same testbench. However the sim results were totally different. Most of the nodes are not toggling at all(seem to be in reset or inhibit state). Anyone with ideas or suggestion? It will be much appreciated..been stuck on this for a while now.    I have tried the sim without the timing file (.sdo) and add +notimingcheck on the ModelSim command VSIM but had no luck.

[Altera_Forum]

--- Quote Start ---  Hi, I'm having some issues with my gate level sim not matching my RTL. I need a gate level sim to gather some toggle rates for power estimation.    The gate level netlist (.vho) is generated from Altera Quartus II software and I plug in the gate level netlist in place of the DUT and keep the same testbench. However the sim results were totally different. Most of the nodes are not toggling at all(seem to be in reset or inhibit state). Anyone with ideas or suggestion? It will be much appreciated..been stuck on this for a while now.    I have tried the sim without the timing file (.sdo) and add +notimingcheck on the ModelSim command VSIM but had no luck.  --- Quote End ---    Hi,  maybe your problem is not simulation related. Did you check your Quartus messages ? Maybe the synthesis tool has some parts of your design removed. Look for things like output stuck a gnd or vcc .  Kind regards  Gerd

[Altera_Forum]

Just check synthesis report and warning messages. but nothing sticks out since the part of the removed or stuck to GND and VCC is expected. 

 I'll keep looking, but thanks for the suggestion.

[Altera_Forum]

--- Quote Start ---  Just check synthesis report and warning messages. but nothing sticks out since the part of the removed or stuck to GND and VCC is expected.   I'll keep looking, but thanks for the suggestion.  --- Quote End ---    Hi Petelu,  do you have a problem with "x" in your gatelevel simulation? Maybe you can try a longer reset sequence, in order to get rid of all the "x". Look carefully how the synthesis tool has the reset implemented. Are all registers connected to the reset signal ?  Kind regards  Gerd

[Altera_Forum]

The design I'm simulating have NIOS core in it. From digging into the waveforms in the gate level netlist, it seem like the NIOS is not functioning in gate level, it does not go through an initialization like RTL sim does