Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Generate HDL QSYS Error

ap1
Beginner
395 Views

Hi

I'm trying to generate a system including HPS(Hard Processor System) of the Cyclone V SoC in Quartus Web Edition Qsys. At the "Generate HDL" stage I got the following errors:

Warning: system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz

Warning: system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz

Warning: system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.

Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender

Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender

Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz

Warning: hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz

Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.

Error: domain_0_default_slave: altera_error_response_slave does not support generation for VHDL Simulation. Generation is available for: Quartus Synthesis, Verilog Simulation.

Error: Generation stopped, 175 or more modules remaining

Error: ip-generate failed with exit code 1: 2 Errors, 8

Warnings Warning: system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz

Warning: system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz

Warning: system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.

Warning: system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz

Warning: system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz

Warning: system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.

Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender

Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender

Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz

Warning: hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz

Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.

Error: Third-party timing and resource estimation model project creation failed: C:/altera/15.0/quartus\bin64/quartus_sh -t quartus_greybox.tcl

0 Kudos
1 Reply
AnilErinch_A_Intel
250 Views

Hi ,

This is a known issue , please find the article below for your reference,

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

Thanks and Regards

Anil


Reply