06-22-2018 05:10 PM
Hi,I have experience with other FPGA manufacturer and respective tools an now I have to send my VHDL code to other entity/person that will run in an INTEL FPGA (Stratix IV). That entity/person has knowledge in INTEL FPGAs and respective tools but I do not intend to send directly the source code, which was written in pure VHDL. Since in the near future I do not see that need to work with INTEL FPGAs, I was thinking the following: To use the Intel Quartus Prime Standard Edition but just the 30-days evaluation period to generate an IP core from my VHDL code; - Is it possible? - Being the IP core generated with Quartus evaluation license, will the generated IP has any limitation (in period of time, or other) ? So, is it possible the to use the generated IP core forever ? - Since, I do not intend to provide the source code, is it possible to encrypt/lock the IP core (even with the Quartus evaluation license) ? Is there any documentation related with this issue, namely limitations with the Quartus 30-days evaluation period and the generation of our own IP cores ? Thanks in advance.
07-02-2018 11:21 AM
--- Quote Start --- What kind of ip core are you trying to provide. The trial version won't produce programming files or time limited IP cores. --- Quote End --- Thank you for your fast reply. I have my own VHDL code (written in pure VHDL) which performs several specific functions of an algorithm. I do not intend to produce programming files (bitstream), I just want to generate an IP from my VHDL code an sent it to other entity. Then, the other entity will receive that IP and integrate it in its project/development. The doubt is the following: with the Quartus 30-days evaluation period, am I able to generate an IP without any limitation (in time or other) ? Therefore, my IP (generated with Quartus 30-days evaluation period) can be used by the other entity (with Quartus licensed) in the next years without any limitation, correct ? Thanks in advance.
07-02-2018 11:56 AM
I think features like partial configuration and netlist generation are only available with a full licence.Any reason you cannot just provide the source code to the 3rd party?
07-02-2018 12:55 PM
--- Quote Start --- I think features like partial configuration and netlist generation are only available with a full licence. Any reason you cannot just provide the source code to the 3rd party? --- Quote End --- IP protection, this is why I want to generate an IP of my VHDL code.