Hi I currently have a simple circuit in a .bdf file. I currently have 4 inputs, some AND gates and one output gate.
I successfully compiled it and generated a University Program VWF to see the waveform simulation. I tested one output with hardcoded inputs with the circuit and the logic works as expected. From here though, I'm not sure whether if I should enter each input manually to get each output or a truth table can be generated.
Thanks for any help.
You can enter each input manually to get the expected output. I don't think Quartus able to generate truth table, usually user have the truth table beforehand to check the design behavior created in Quartus.
If you have the logic expression, you can google find a truth table generator to generate for you.
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