Re: Generating a netlist for individual project components or modules - Intel Community

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Generating a netlist for individual project components or modules

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Hello,

Using Quartus, I know how to generate a functional simulation netlist for the whole design. But is there a way to generate a netlist for (only) a specific component / module inside the hierarchy ?

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Nope. what u can do is set those module as the top level and virtual pin all.

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