Getting 'TCL READ VARNAME' error message while simulating.

[junaid]

Successfully compiled n-bit shift register Design & Test bench codes (Verilog).

But, as tried for RTL simulation , it throws an error by stating a message as below

Error: Error: NativeLink simulation flow was NOT successful.

There was no issue with the simulator (simulation worked for previous designs).

Help me to solve this issue.

These are the error messages I've got so far,

Error: TCL READ VARNAME
Error: Error: NativeLink simulation flow was NOT successful
Error (23031): Evaluation of Tcl script c:/intel_fpga/16.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 3 errors, 1 warning
Error: Peak virtual memory: 4835 megabytes
Error: Processing ended: Mon Jun 14 11:06:54 2021
Error: Elapsed time: 00:00:45
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus Prime Flow was unsuccessful. 5 errors, 2 warnings

I would like to appreciate your time and consideration,

Thanks & Regards

JUNAID.K
 

[Nurina]

Hi,

Are you using Standard edition? This error is something that can be ignored: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2018/error--23031---evaluation-of-tcl-script--intel-quartus-prime-sys.html

Regards,

Nurina

[Nurina]

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.