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Getting platform designer to find `include files

JBoot1
Beginner
810 Views

How do you get platform designer to generate the proper tcl files so that when a verilog file has an include statement the file is found for both synthesis and simulation? This question has been asked before (see below link), but never answered.

 

https://forums.intel.com/s/question/0D50P00003yyOg6SAE/getting-qsys-to-find-h-and-vh-files?language=...

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1 Reply
Kenny_Tan
Moderator
110 Views

​In the platform designer, you can add those file

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer...

 

page 566

 

Set to the correct output_files where you want to store it. Then the path of this include have to be same for your output_files so that quartus able to synthesis it.

 

 

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