Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Getting platform designer to find `include files

JBoot1
Beginner
‎10-23-2018 01:13 PM
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How do you get platform designer to generate the proper tcl files so that when a verilog file has an include statement the file is found for both synthesis and simulation? This question has been asked before (see below link), but never answered.

 

https://forums.intel.com/s/question/0D50P00003yyOg6SAE/getting-qsys-to-find-h-and-vh-files?language=en_US

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Kenny_Tan
Moderator
‎10-25-2018 05:30 AM
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​In the platform designer, you can add those file

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf

 

page 566

 

Set to the correct output_files where you want to store it. Then the path of this include have to be same for your output_files so that quartus able to synthesis it.

 

 

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