How do you get platform designer to generate the proper tcl files so that when a verilog file has an include statement the file is found for both synthesis and simulation? This question has been asked before (see below link), but never answered.
In the platform designer, you can add those file
Set to the correct output_files where you want to store it. Then the path of this include have to be same for your output_files so that quartus able to synthesis it.