Glitches in I/O signals & PLL implementation

Altera_Forum · ‎02-11-2011

Hi all

I am working on a repeater implementation. The code is working fine but am having a grave problem. I am getting some (random) glitches in the output simulations which are even smaller than 50% cycle of the clock used. I am very confused on guessing what can be the factors for such glitches. Can it be the fact that am using Timing simulation for simulating the waveform ( I am using Quartus II 8.0 because I feel comfortable using waveform files than testbenches.)

I am using Cyclone III FPGA with 24MHz frequency.

Second issue with code is the pll implementation. I am generating a secondary internal clock of 1.5 MHz using pll. But somehow, there is no output of the pll. I have already tried and simulated the pll in ModelSim and its working fine there. But when i try to integrate the pll to the code, its not working.

Any inputs are welcome !

Vikram

Altera_Forum · ‎02-11-2011

Are you using a fully synchronous code? Latches or combinatorial code on the output could create that kind of glitches.

For the pll, is the input clock in the right frequency range? How is the pll's locked output?

Altera_Forum · ‎02-11-2011

Are you using a fully synchronous code? Latches or combinatorial code on the output could create that kind of glitches.

For the pll, is the input clock in the right frequency range? How is the pll's locked output?

no, am working on making those ;). have shared the particular file which is making problems. sorry for bad coding style !

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;  
ENTITY start IS
	
	PORT
	(data_sent,encoder_enable 	: in std_logic;
		clk,data_ready,master_slave,reset_system: in STD_LOGIC;
		counter_en,reset,reset_sel,counter_en_sel	: out	STD_LOGIC;
		counter_in       :out std_logic_vector(8 downto 0) ;
		status	         :out std_logic_vector(4 downto 0);					
		f_code	         :in std_logic_vector(3 downto 0)	);
END start;
ARCHITECTURE project OF start IS
TYPE state IS (zero,one,two); 
SIGNAL pr_state, nx_state: state;
signal status1 : std_logic_vector(4 downto 0); 
begin
-------------lower section
lower_sec: process (reset_system,clk)
begin
  if  reset_system='1' then pr_state <=zero; elsif
    (clk'event and clk='1') then pr_state <= nx_state;
   end if;
end process;
-------------upper section
upper_sec: process (pr_state,data_ready,clk)
variable temp_master_slave: std_logic;
variable temp_fcode:std_logic_vector(4 downto 1);			
begin
	
	CASE pr_state IS
	
		WHEN zero =>
	
				counter_en<='0'; counter_en_sel<='0'; 
				reset<='1';status1<="00000";counter_in<=conv_std_logic_vector(0,9);
				reset_sel<='1'; 
		
				
				if encoder_enable ='1' and  data_ready='1' then 
				temp_master_slave:=  master_slave; 
 					temp_fcode:=f_code;
					status1(0)<=f_code(0);
					status1(1)<=f_code(1);
					status1(2)<=f_code(2);
					status1(3)<=f_code(3);
					status1(4)<=master_slave;
				if temp_master_slave='1' then counter_in<=conv_std_logic_vector(37,9); 
				elsif temp_fcode="0000" then counter_in<=conv_std_logic_vector(37,9); 
				elsif temp_fcode="1000" then counter_in<=conv_std_logic_vector(37,9);
				elsif temp_fcode="1101" then counter_in<=conv_std_logic_vector(37,9);
				elsif temp_fcode="1110" then counter_in<=conv_std_logic_vector(37,9);
				elsif temp_fcode="1111" then counter_in<=conv_std_logic_vector(37,9);
  				elsif temp_fcode="1001" then counter_in<=conv_std_logic_vector(37,9);
				
				elsif temp_fcode="0001" then counter_in<=conv_std_logic_vector(53,9);
				elsif temp_fcode="0010" then counter_in<=conv_std_logic_vector(85,9); 
				
				elsif temp_fcode="0011" then counter_in<=conv_std_logic_vector(157,9);
				
				elsif temp_fcode="0100" then counter_in<=conv_std_logic_vector(301,9);
				elsif temp_fcode="1100" then counter_in<=conv_std_logic_vector(301,9);
				
				end if;
				
				nx_state<=one;	else status1<="00000";counter_in<=conv_std_logic_vector(0,9);
				nx_state<=zero; end if;
		WHEN one =>
				counter_en<='0'; counter_en_sel<='0';   			 
  				reset<='1';
				reset_sel<='1';
				nx_state<=two;
		WHEN two =>
				counter_en<='1'; counter_en_sel<='1'; 
				reset<='0';
				reset_sel<='0';
				if data_sent='1' then nx_state<=zero; else nx_state<=two; end if;
	end case;
end process;
		
status <= status1; 
	
END project;

i have narrowed down latches to this particular file.

as for pll, i am still working on it !

thanks

Vikram

Altera_Forum · ‎02-11-2011

The state machine outputs are decoded by combinational logic from present state. That's a standard Moore FSM scheme, but to get glitch free outputs, they have to be registered.

P.S.: I see, that you are also processing other signals (Mealy scheme) and have latches in the code. But glitches can be generated even by the basic decoder, so registering the outputs would be better anyway.