Hello,
the below small problem of filtering the leading bit of a bit vector could be perfectly implemented with one LE per bit, utilizing the carry chain respectively arithmetic mode of Cyclone III. But Quartus apparently doesn't want to, uses more LEs and ends up with a rather slow and ineffective solution. 84 LEs/25.4 ns tpd compared to 64 LEs/12.9 ns using the carry chain. My guess is, that Quartus isn't prepared to use the carry chain for non-arithmetic problems.
But the fast solution can be enforced by using cycloneiii_lcell_comb, most likely also with other low level coding styles. Does anyone know how to achieve this in behavioral code like below?
Frank
The problem has been motivated by an edaboard thread, by the way:
http://www.edaboard.com/thread201958.html library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity leading_bit is
generic(
NBIT: INTEGER :=64
);
port (datain: std_logic_vector (NBIT-1 downto 0);
dataout: out std_logic_vector(NBIT-1 downto 0)
);
end entity;
architecture rtl of leading_bit is
BEGIN
PROCESS (datain)
variable carry: std_logic;
BEGIN
carry:='0';
FOR I IN NBIT-1 DOWNTO 0 LOOP
dataout(I) <= datain(I) AND NOT carry;
carry:=carry OR datain(I);
END LOOP;
END PROCESS;
END;
