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Global assignment being deleted/changed when using same source in multiple VHDL libraries.

Hi there,

I have an entity in a file which is compiled into two different VHDL libraries. I also have two different packages with the same name, for each library which are input into the entity. When I synthesis the design, it builds fine the first time. However when I rerun the design, it fails. The failure seems to be either the result of picking up the wrong package to feed to the wrong entity. I am not sure how/why this happens and only happens on reruns. When I manually (through the TCL console) remove_all_global_assignments and rerun the design, it works. So removing the assignments kind-of resets the sources/libraries - this assuming that something went wrong with them in the first place (?).

Any ideas or comments or solutions?

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Could you provide the design.qar and steps to reproduce the error? What is the software edition and version you are using?




I will have to request authorisation for that, supplying anything else but the source is ok.

But in the meantime let me furnish you with as much detail as possible.

  • Using, Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition.
  • Its a design which has several VHDL libraries (no work library), let's call them A, B and C
  • Most of the files are compiled into library B, top in in library A and a small set of files are in library C
  • 3 files are compiled both in library B and library C
  • Packages (let's call P) of the same name and records (let's call R) are compiled into library B and library C. Each library's record R is different, in terms of members, sizes etc.
  • The 3 files use this package/record and so implement different things although they share files and package/record names
  • In top ... each package/record/entity is referred to by its library prefix, for example ... B.entityWithSameName or C.entityWithSameName .... signal w_b : B.recordWithSameName; ... etc.
  • Compiling through the GUI works fine (only when I build all, but this is acceptable as I have some pre flow scripts etc.)
  • Compiling through command line (quartus_sh) only works the first time - we have a modified version of a quartus.tcl script which executes the flow ... I will minimise it and include that here. Presumably something is missing from this TCL script (?), executed using quartus_sh -t <tcl>.
# Copyright (C) 1991-2013 Altera Corporation ... # project is open here   set MAX_ATTEMPTS [expr [lindex $argv 1]] source quartus.qsf export_assignments   set attempt 0 while {$attempt < $MAX_ATTEMPTS} { set attempt [expr {$attempt + 1}] execute_flow -compile if { violations in timing ...} { puts "Timing OK. No violation found." break } else { if {..maximum attempts...} { break } else { # rerun ... delete firmware RBF file # removing assignments to ensure library mapping can be reset # remove_all_global_assignments -name VHDL_FILE } } }
  • I have really minimised the above, kindly excuse if something obvious is missing (just to be clear I didn't write it, so it could have mistakes!).
  • How does the problem exhibit itself. From the messages generated I can not see any difference from two consecutive runs except when the problem happens. I will try to explain best I can. On the second run, during analysis and synthesis, when the compiler hits the entity in library B inside top (B.entityWithTheSameName) ... it picks up the package from the other file. I know this because there is a warning for unused variable in the package and instead of saying Warning at fileBWithSameNamePackage,vhd, it says Warning at fileAWithSameNamePackage.vhd - almost as if it had lost the library namespace somehow and picked up the first file with the package in it. A record in the package is input into the entity, so the errors complain about "Error (12002): Port "..." does not exist in macrofunction". And so on the error compounds onto other things.


A few other points:

  • At the end of first run, I can see the library mappings are correct by looking at the map.rpt file, all files are correctly placed in A and B.
  • Obviously second run does not finish and I cannot verify how this has gone wrong.
  • I attempted to reassign library mappings, so I executed remove_all_global_assignments -name VHDL_FILE between runs, that fixed the second run but the third failed (again I wasn't exactly sure what I was doing there).
  • If there was a way to (correctly) query whether the global assignment for the files to libraries is correct, that would help is knowing that the problem has happened. And to correct it, how to overwrite these assignments by the correct ones.





You have to ensure that you use a distinct VHDL Namespace for Each Library. For the Example RTL, the analyzer searches all libraries in an unspecified order until the analyzer finds package utilities_pack and uses items from that package. If another library, for example projectLib also contains utilities_pack, the analyzer may use this library instead of myLib.utilites_pack if found before the analyzer searches myLib.


Therefore, you have to change the name to a unique name.




Right thanks for that explanation, perhaps I can explain deeper and maybe it relates to what you are saying. But before I do, would your explanation justify the design compiling fine the first time and not the second?


Anyway here's a more detailed look at the VHDL files themselves.

I have a orderbook entity which accepts input t_messages record.

Two different records with the same t_messages name are defined in two packages with the same name orderbook_pkg - in different files, .e.g pkgA.vhd and pkgB.vhd.

The orderbook entity (file) has use work.orderbook_pkg and uses orderbook_pkg.t_messages. Note no library specification as work should denote the current compiling context/workspace (please correct me if I misunderstand this).

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.orderbook_pkg;   entity orderbook is port( i_messages : in orderbook_pkg.t_messages; ...

LibA is compiled with orderbook file + pkgA.vhd

LibB is compiled with orderbook file + pkgB.vhd

set_global_assignment -name VHDL_FILE pkgA.vhd -library LibA set_global_assignment -name VHDL_FILE orderbook.vhd -library LibA set_global_assignment -name VHDL_FILE pkgB.vhd -library LibB set_global_assignment -name VHDL_FILE orderbook.vhd -library LibB

top is compiled in another MainLib (no work libs in this project)

top creates signals for the messages:

library LibA; library LibB; ... signal msgA : LibA.orderbook_pkg.t_messages; signal msgB : LibB.orderbook_pkg.t_messages;

top also instantiates the two entities using library names:

libAEntity : entity LibA.orderbook(rtl) port map( i_messages => msgA, ... ... libBEntity : entity LibB.orderbook(rtl) port map( i_messages => msgB, ...

It compiles fine the first time from a clean start. A clean start means if you remove all the files in the db directory. However, without cleaning the db directory, on a second rerun when its compiling libBEntity:LibB.orderbook it picks up pkgA.orderbook_pkg.

Info (12129): Elaborating entity "orderbook" using architecture "A:rtl" for hierarchy "orderbook:libBEntity" File: C:/temp/top.vhd Line: 1567 Warning (10542): VHDL Variable Declaration warning at pkgA.vhd(346): used initial value expression for variable "v_dummy" because variable was never assigned a value File: C:/temp/pkgA.vhd Line: 346 ... ... Error (12002): Port "i_messages.orderB.eom" does not exist in macrofunction "libBEntity" File: C:/temp/top.vhd Line: 1567 Error (12002): Port "i_messages.orderB.eop" does not exist in macrofunction "libBEntity" File: C:/temp/top.vhd Line: 1567 ...

And eventually falls over because the records/ports are different.

Hopefully I have summarised this, if you can assess the method I am using based on your previous explanation - hopefully you can confirm or deny that it is the same case. Note it passes with a clean db directory - which is the current workaround that I am using. Thank you for you help.




In the Intel Quartus Prime Standard edition software, the analyzer searches all libraries in an unspecified order until the analyzer finds package. This means that it will use the package it found first disregards of the library specified in the HDL file.


It is different from the Pro edition where the analyzer will use the package as specified.


You may refer the comparison in






May I know if you have other questions?




Yes thank you, you may close the case.