Good technique for designing FSM

[Altera_Forum]

Hello guys, 

 Suppose I have the following behaviour of a circuit and I wanna design a FSM to control it: https://www.alteraforum.com/forum/attachment.php?attachmentid=6674  in each clock cycle, red block means say...multiplication, blue block means addition and green block means certain output after comparison.   I can generally think of two ways to construct the FSM: 1) I have two states so as to toggle between red and blue blocks, in addition a counter is set up, after four clock cycles the state that triggers blue blocks will also trigger green block, a third state is used after eight cycles and output green blocks only.   2) I use 4 states, triggering blue only; red only; blue&green; green only. One counter is needed to determine which state to go next.  I'm not sure after compilation which FSM will produce more efficient circuit, or maybe they are the same thing? Is there any typical technique used to construct FSM that control the behaviour similar to the above example?  Thanks!

[Altera_Forum]

If there is always the same number of blue, red, and greens, you could also; 

 1) Use three states; blue, red, and end 2) Use a counter that counts from 0 to 3, or from 3 to 0. 3) Use the blue, red states and the counter to count out the first eight states, i.e., the first four pairs of blue+red states 4) Reuse the counter to count the four end states 5) Use the blue state to generate the enable to the blue logic 6) Pipeline the blue enable by 1 clock to generate the red enable (or use the red state) 7) Pipeline the blue or red enable to generate the green enable  Using pipelined signals to generate the outputs can simplify the state machine logic.  Cheers, Dave