HDL -vs- schematic entry

[Altera_Forum]

Howdy! 

 So here's a question: My current design is based around ye olde epf10k10 with a whopping 576 LE's. Needless to say, I'm now up to 91% on my LE count. Has anyone ever done any tests as to the efficiency between HDL languages and schematic entry? I'll run some tests this weekend but having done 74xx designs by hand (showing my age) I'd venture to say I should be able to get some of the counts down.  As an aside, I actually reduced my LE count from 525 to 514 by adding an extra bit to my state machine, going from 4- to 5-bits.  IIRC schematics are just translated to HDL and then compiled but does that mean 'manual' construction makes any difference at all?  -Mux

[Altera_Forum]

In HDL, you can code a hierarchy for every primitive in a schematic and hook them up, thereby creating the same thing. So just switching to schematic will not buy you anything. Now, when you take your state-machine and convert it to a schematic, it won't be a 1:1 translation, and it could be smaller. (Although it could be larger, and even if it does become smaller there's a good chance the same thing could be done in HDL).  

I find it very difficult to reduce area without removing functionality. The places to look are: - Seeing if something can be done a different way. As an example, if you had a wide and long shift-register, say 16 bits wide and 20 bits deep, that takes up a ton of registers. You can build a shift-register out of a memory block that is much smaller. (Quartus does this automatically assuming there isn't an asynchronous reset, and based on the size of your design I don't think you have anything like this, it's just an example) - The other case is when you write more abstract code like a case statement, there might be some behavior that is inferred which you don't want. It's just worthwhile to study it and see if you might be able to reduce it through some options. But again, these are usually small changes that are almost in the noise of the design.

[Altera_Forum]

I guess that both schematic and HDL are translated into some internal data format. 

 With HDL you can write your code with different levels of abstraction. If you use a low level of abstraction, HDL coding is no fun at all... At a higher level, it is often not clear how things will be translated into LEs by Quartus (or at least, Quartus has a different opinion than the designer ;-) and it is hard to estimate how many ressources you will need. In schematic design however, it is normally easy to see how Quartus will map this to the LEs. Also in my experience, lpm_counters (or MegaWizard generated ones) are more efficient than counters from VHDL code.  So if you want to optimize the design for area, I would stay with the schematic entry.  Other notes: - At least with newer Quartus version, there is the option to translate a schematic design into VHDL (File -> Create / Update -> Create HDL File...) So you can than compile your VHDL file to see if there is some magic. There won't be. - I guess you know the "auto pack register" option? (Did this exist also for FLEX10K? Long ago, I am not sure...)  Regards,  Thomas  www.entner-electronics.com - Home of the EEBlaster (EUR 49,-)