count 4 clock cycles

[Altera_Forum]

Hi ,  

i want to design counter that count 4 clock cycles for every rise of the pulse And_out .   i wrote it at process but the output of signal count is always 0 .   --process# 3 - counter 4 numbers at each rise of And_out process (ResetP,clk_100M,And_out)  begin   if ResetP = '1' then   count <= 0 ; else  if And_out'event then  if ( clk_100M'event and clk_100M='1' ) then   if (count < 4) then  count <= count + 1;  else   count <= 0 ;  end if ;  end if ;   end if ; end if ; end process;  is it legal to write it this way ?  picture Design attached.

[Altera_Forum]

It doesn't look good. You should make a synchoronous design. 

 To detect de rise of a signal you may write:  process.. ..  if(clk'event and clk = '1') then  q_reg <= q_next;  end if...  q_next <= And_out;  rise <= And_out and not q_reg;  when rise is '1' it means that And_out was '0' and now has a '1' ( rising edge ).  the counter:  proces...  if(clk'event and clk='1' )then  c_reg <= c_next;  end if; ...   c_next <= c_reg + 1 when ( c_reg = "00" and rise = '1' ) else  c_reg when ( c_reg = "00" ) else  c_reg + 1 when ( c_reg < 3 ) else  "00";  or something like this.

[Altera_Forum]

Hi bertulus ,  

The first part the logic gate output i did same as you , at my photo i call to the signal And_out and you called it rise .  About the second part - counter , i have some questions :  1.Does the process end after end if as mentioned below ? and the last 4 lines arent at the process ?  proces... if(clk'event and clk='1' )then c_reg <= c_next; end if; end process ;  2.At the process c_reg is the output of the F.F and c_next is the input of the F.F ,  after that c_next ( input ) gets c_reg (output) as mentioned below, why does the signal returns back to the input ?   c_next <= c_reg + 1 when ( c_reg = "00" and rise = '1' ) else c_reg when ( c_reg = "00" ) else c_reg + 1 when ( c_reg < 3 ) else "00";  3.does c_next means count and rise means and_ out at my attached photo design?  4.i didn't understand the condition :   c_next <= c_reg + 1 when ( c_reg = "00" and rise = '1' ) else c_reg when ( c_reg = "00" ) else c_reg + 1 when ( c_reg < 3 ) else "00";  why does c_next gets c_reg+1 when ( c_reg = "00" and rise = '1' ) ? c_reg is std_logic of one bit only , why does it has to be equal to "00" in order that the counter will inc by 1 ?  I did not understand the following conditions as well ...   can you please explain each step please ?  my design purpose is that for every time that the And_out signal rise for '1' the counter need to count 4 clocks and when he finish the counting he gets 0 and wait for the next pulse .  Thanks .

[Altera_Forum]

Hi odedidush, 

 About the second part - counter , i have some questions : 1.Does the process end after end if as mentioned below ? and the last 4 lines arent at the process ?  proces... if(clk'event and clk='1' )then c_reg <= c_next; end if; end process ;  the complete code should be:  process(reset, clk) begin  if( reset = '1' ) then  c_reg <= "00";  elsif( clk'event and clk = '1' ) then  c_reg <= c_next;  end if; end process;  2.At the process c_reg is the output of the F.F and c_next is the input of the F.F , after that c_next ( input ) gets c_reg (output) as mentioned below, why does the signal returns back to the input ?    i answer on the 4th question.  3.does c_next means count and rise means And_ out at my attached photo design?  c_reg means count and rise and_out.  4.i didn't understand the condition :  c_next <= c_reg + 1 when ( c_reg = "00" and rise = '1' ) else c_reg when ( c_reg = "00" ) else c_reg + 1 when ( c_reg < 3 ) else "00";  why does c_next gets c_reg+1 when ( c_reg = "00" and rise = '1' ) ? c_reg is std_logic of one bit only , why does it has to be equal to "00" in order that the counter will inc by 1 ?  I did not understand the following conditions as well ...  can you please explain each step please ?  my design purpose is that for every time that the And_out signal rise for '1' the counter need to count 4 clocks and when he finish the counting he gets 0 and wait for the next pulse .  i code it that way because a sequencial circuit has 2 parts: the flip-flops and the combinational next-state logic. you can mixed both coding in one block ( one process ) or split them between the register block ( process with c_reg <= c_next ) and the next state logic in other block ( you can use another process or concurrent statements ). for me it's a more clear way to describe circuits.   as c programmers we prefer one block of code and thinking register are variables. but when the design doesn't work or are some little failures it's imposible to find the reason. working with 2 blocks of code you're sure that your vhdl description match a digital circuit you can build with rtl components ( mux, comparators, adders, etc ).  i control c_next this way:  a - the trigger condition: c_reg = "00" ( stoped ) and rise = '1' ( trigger ). i incremented c_reg so counting begins on next rising edge of clk.  b - no trigger condition counter not counting: this assigment take place if previous condition don't match. the counter stuck at "00". i copied c_reg on itself. assign "00" will be more clear.  c - counting: i assigned c_reg + 1 when the c_reg is 1 or 2 ( c_reg < 3 ). this will increment c_reg on next rising edge of clk.  d - reach 3: when c_reg reach 3 the next value will be "00". you'll go to state b and the counter stuck until condition a meets.    

[Altera_Forum]

thanks for your explanations bertulus .