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HDMI IP Core generation mode settings using Quartus 15.1

Altera_Forum
Honored Contributor II
‎12-28-2015 08:00 AM
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I have generated HDMI IP core using Quartus version 15.1. I have generated sink IP (Receiver) and connected our source VIP with that. 

 

The output mode signal was "0" which means DVI is set, How can I change the setting from DVI mode to HDMI mode. 

As per the specification, EDID contains the information regarding the mode: DVI or HDMI. 

How can we fill the EDID memory to specify the above information or are there some other setting to specify the above.
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Altera_Forum
Honored Contributor II
‎12-28-2015 11:48 PM
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The EDID information is typically read from the display over an I2C link. It is implemented as an I2C memory device. Search for VESA EDID on the internet to find documentation of the data provided in the I2C memory device.

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Altera_Forum
Honored Contributor II
‎12-29-2015 05:03 AM
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--- Quote Start ---  

The EDID information is typically read from the display over an I2C link. It is implemented as an I2C memory device. Search for VESA EDID on the internet to find documentation of the data provided in the I2C memory device. 

--- Quote End ---  

 

 

Hi Galfonz, 

 

Yes, you are right that we can read the EDID information through I2C interface. I read address 14h from HDMI Core IP SCDC interface, but all values are 00h. 

Also I want to change the mode from DVI to HDMI in Altera HDMI IP core. Is there any way to set this in HDMI IP core. 

 

It will be helpful if you could explain how to switch mode from DVI to HDMI. 

Also could you confirm that after extracting the HDMI sink module, EDID memory is initialized to default values (as specified by the EDID spec.) or not? 

 

Thanks & Regards, 

Manish
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Altera_Forum
Honored Contributor II
‎12-29-2015 11:32 PM
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I've not worked with the HDMI IP from Altera, so I can't help you with that.

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Altera_Forum
Honored Contributor II
‎01-13-2016 04:10 AM
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Do you know how to get contact for Altera HDMI Core IP queries.

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Altera_Forum
Honored Contributor II
‎03-26-2018 10:58 AM
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Hello manishchand, did you get the core to work at the end? 

I am currently having problems reading SCDC offset 0x40, only clock is locked but not the 3 data channels, any similar experience? 

Thanks in advance!
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