HELP with Verilog for a binary coded decimal converter

Altera_Forum · ‎03-19-2013

im trying to make a BCD converter with 5 input but there is something wrong with what I have here. please assist.

module Lab08 (x, d);

input [4:0] x;

output [7:0] d;

m0 = 5'b00000;

m1 = 5'b00001;

m2 = 5'b00010;

m3 = 5'b00011;

m4 = 5'b00100;

m5 = 5'b00101;

m6 = 5'b00110;

m7 = 5'b00111;

m8 = 5'b01000;

m9 = 5'b01001;

m10 = 5'b01010;

m11 = 5'b01011;

m12 = 5'b01100;

m13 = 5'b01101;

m14 = 5'b01110;

m15 = 5'b01111;

m16 = 5'b10000;

m17 = 5'b10001;

m18 = 5'b10010;

m19 = 5'b10011;

m20 = 5'b10100;

m21 = 5'b10101;

m22 = 5'b10110;

m23 = 5'b10111;

m24 = 5'b11000;

m25 = 5'b11001;

m26 = 5'b11010;

m27 = 5'b11011;

m28 = 5'b11100;

m29 = 5'b11101;

m30 = 5'b11110;

m31 = 5'b11111;

assign d23 = 0;

assign d22 = 0;

assign d21 = m20|m21|m22|m23|m24|m25|m26|m27|m28|m29|m30|m31;

assign d20 = m10|m11|m12|m13|m14|m15|m16|m17|m18|m19|m30|m31;

assign d13 = m8|m9|m18|m19|m28|m29;

assign d12 = m4|m5|m6|m7|m14|m15|m16|m17|m24|m25|m26|m27;

assign d11 = m2|m3|m6|m7|m12|m13|m16|m17|m22|m23|m26|m27;

assign d10 = x0;

endmodule

Altera_Forum · ‎03-19-2013

here is my original before I trying making it fancier. (I hope it helps)

module Lab08 (x4, x3, x2, x1, x0, d23, d22, d21, d20, d13, d12, d11, d10);

input x4, x3, x2, x1, x0;

output d23, d22, d21, d20, d13, d12, d11, d10;