HOLD timing violation

[Altera_Forum]

I am using timequest and getting a hold timing violation. the launch clock is a 10MHz clock generated from a PLL. the latch clock is 50MHz (from which the 10MHz is derived). my logic is doing an edge detection on the "from" signal in the "to" domain. in other words, i am using the 50MHz clock to edge detect on a 10MHz signal. I do not understand why there is a hold violation. any suggestions? 

 thanks kevin

[Altera_Forum]

You need to use synchronizer from 10 MHz to 50 MHz. Also, this is a flase path.

[Altera_Forum]

why would it be a false path? the 10MHZ clock is generated from the 50MHz clock with a PLL? the clocks are related.  

 for synchronization, i do an edge detect with the 50MHz clock on the 10MHz signal. this should be just fine. it's like sampling an asynchronous input. we do it all the time.

[Altera_Forum]

Sorry about false path. It should be a derived clock.