Having outputs changes behavior

[Altera_Forum]

Why would having outputs change the behavior of a circuit? I'm trying to test whats going on so I put in test outputs to read signals however the behavior of the circuit is different when I have the outputs from when I don't have them making it impossible to tell what's going on.

[Altera_Forum]

Just one explanation would be that you have errors in your logic which would cause parts of the circuit to be synthesized out, but when you add outputs as test points those parts would be put back in by the compiler. 

 Try to use signal probe or signaltap, or better run a simulation in modelsim.

[Altera_Forum]

My guess is you have a timing problem. It's not bringing the signals out that's causing the problem, it's the fact that you have a different fit and therefore different timing. That's usually what the problem is in those situations, and they're a pain to debug for that very reason(SignalTap and SignalProbe can be run on post-fit netlists, which is harder to work with, but allows you to get around this issue.)