I'm trying to design a multicycle unpipelined processor and I'm running into some timing issues.
I've attached the waveforms that I've been getting, none of them are quite right. Basically it works like this, on the clock edge the control is in the fetch stage, during this stage it puts fetchEn high, fetchEn is an enable single for a latch which on a clock edge passes the program counter through to the instruction memory and gets an instruction on the next clock edge. Also on the next clock edge I'm in the decode stage where I set decodeEn high which enables the latch between the instruction and register file. The problem is, in the best case (Control on the rising edge, Latches on falling edge) the decodeEn gets fired at the same time as my instruction becomes available (functional simulation). I think that I actually need my instruction to be available sooner, like a half cycle but I'm not quite sure how. I think I'm going to have to just introduce another cycle in between fetch and decode.
Thoughts?
http://img520.imageshack.us/img520/6172/waveszm2.jpg
