Hello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.

[ACoga]

Most of the signals relate to NIOS. The design based on a single 100MHz clock. There is an additional clock 12.5MHz generated in pll in QSYS and connected only to epcs flash controller. I've seen similar connection of the epcs flash controller in some examples.

I get no setup time violations and functionally everything works fine. But I can't get rid of hold time violation warnings. See the attached TimeQuest Report. Please help.

Thank you.

[KhaiChein_Y_Intel]

Hi, Have you try the constraints? What is the result in the newer version? Thanks.