Hello.
I'm using ALT_IOBUF in a bdf file to get a bidir data bus.
I have instantiated one primitive, connected the 'o' to the data_in[31..0] of my block, the 'i' to the data_out[31..0] of my block, the 'oe' to the data_oe (single signal) that drive the direction and the 'io' to the bidir data_bus[31..0] outgoing from my design file.
I have also settled the parameter NUMBER_OF_CHANNEL to 32 in the primitive instantiated.
When I compile with QII 7.2 and a standard set of assignments, get the error:
Error: Width mismatch in data_bus[31..0] -- source is ""io" (ID ALT_IOBUF:mc_data_buf)"
Error: Width mismatch in port "i" of instance "mc_data_buf" and type ALT_IOBUF -- source is ""data_out[31..0]""
Error: Width mismatch in port "io" of instance "mc_data_buf" and type ALT_IOBUF -- source is ""data_bus[31..0]""
and so on...
Can I use a single primitive to connect buses? Why get that errors?
Thanks
EDIT:
Solved. It's not possible to use ALT_IOBUF between blocks or module inside the design because is only for pin chip buffering. Used TRI and WIRE instead.
